Commit 9037d802 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: refactor bw related variable structure in val_ctx 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ac5c2947

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

+9 −9
Original line number Diff line number Diff line
@@ -2557,7 +2557,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, 
 */

static bool is_display_configuration_supported(

	const struct bw_calcs_vbios *vbios,

	const struct bw_calcs_output *calcs_output)

	const struct dce_bw_output *calcs_output)

{

	uint32_t int_max_clk;
@@ -2568,7 +2568,7 @@ static bool is_display_configuration_supported( 


	int_max_clk = bw_fixed_to_int(vbios->high_sclk);

	int_max_clk *= 1000; /* MHz to kHz */

	if (calcs_output->required_sclk > int_max_clk)

	if (calcs_output->sclk_khz > int_max_clk)

		return false;



	return true;
@@ -2790,7 +2790,7 @@ bool bw_calcs(struct dc_context *ctx, 
	const struct bw_calcs_vbios *vbios,

	const struct pipe_ctx pipe[],

	int pipe_count,

	struct bw_calcs_output *calcs_output)

	struct dce_bw_output *calcs_output)

{

	struct bw_calcs_data *data = dm_alloc(sizeof(struct bw_calcs_data));
@@ -2831,20 +2831,20 @@ bool bw_calcs(struct dc_context *ctx, 
					bw_int_to_fixed(1000)));

		calcs_output->blackout_recovery_time_us =

			bw_fixed_to_int(data->blackout_recovery_time);

		calcs_output->required_sclk =

		calcs_output->sclk_khz =

			bw_fixed_to_int(bw_mul(data->required_sclk,

					bw_int_to_fixed(1000)));

		calcs_output->required_sclk_deep_sleep =

		calcs_output->sclk_deep_sleep_khz =

			bw_fixed_to_int(bw_mul(data->sclk_deep_sleep,

					bw_int_to_fixed(1000)));

		if (yclk_lvl == 0)

			calcs_output->required_yclk = bw_fixed_to_int(

			calcs_output->yclk_khz = bw_fixed_to_int(

				bw_mul(low_yclk, bw_int_to_fixed(1000)));

		else if (yclk_lvl == 1)

			calcs_output->required_yclk = bw_fixed_to_int(

			calcs_output->yclk_khz = bw_fixed_to_int(

				bw_mul(mid_yclk, bw_int_to_fixed(1000)));

		else

			calcs_output->required_yclk = bw_fixed_to_int(

			calcs_output->yclk_khz = bw_fixed_to_int(

				bw_mul(high_yclk, bw_int_to_fixed(1000)));



		/* units: nanosecond, 16bit storage. */
@@ -3245,7 +3245,7 @@ bool bw_calcs(struct dc_context *ctx, 
		calcs_output->cpup_state_change_enable = true;

		calcs_output->stutter_mode_enable = true;

		calcs_output->dispclk_khz = 0;

		calcs_output->required_sclk = 0;

		calcs_output->sclk_khz = 0;

	}



	dm_free(data);

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+39 −40
Original line number Diff line number Diff line
@@ -470,17 +470,17 @@ static void dcn_dml_wm_override( 
	a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);

	a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);



	context->watermarks.a.cstate_pstate.cstate_exit_ns =

	context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =

			a.cpstate.cstate_exit_us * 1000;

	context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

	context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

			a.cpstate.cstate_enter_plus_exit_us * 1000;

	context->watermarks.a.cstate_pstate.pstate_change_ns =

	context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =

			a.cpstate.pstate_change_us * 1000;

	context->watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;

	context->watermarks.a.urgent_ns = a.urgent * 1000;

	context->watermarks.b = context->watermarks.a;

	context->watermarks.c = context->watermarks.a;

	context->watermarks.d = context->watermarks.a;

	context->bw.dcn.watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;

	context->bw.dcn.watermarks.a.urgent_ns = a.urgent * 1000;

	context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;

	context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;

	context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;





	for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
@@ -543,28 +543,28 @@ static void calc_wm_sets_and_perf_params( 
		v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;

		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);



		context->watermarks.b.cstate_pstate.cstate_exit_ns =

		context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =

			v->stutter_exit_watermark * 1000;

		context->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =

		context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =

				v->stutter_enter_plus_exit_watermark * 1000;

		context->watermarks.b.cstate_pstate.pstate_change_ns =

		context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =

				v->dram_clock_change_watermark * 1000;

		context->watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

		context->watermarks.b.urgent_ns = v->urgent_watermark * 1000;

		context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

		context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;



		v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;

		v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;

		v->dcfclk = v->dcfclkv_nom0p8;

		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);



		context->watermarks.c.cstate_pstate.cstate_exit_ns =

		context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =

			v->stutter_exit_watermark * 1000;

		context->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =

		context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =

				v->stutter_enter_plus_exit_watermark * 1000;

		context->watermarks.c.cstate_pstate.pstate_change_ns =

		context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =

				v->dram_clock_change_watermark * 1000;

		context->watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

		context->watermarks.c.urgent_ns = v->urgent_watermark * 1000;

		context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

		context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;

	}



	if (v->voltage_level < 3) {
@@ -578,14 +578,14 @@ static void calc_wm_sets_and_perf_params( 
		v->dcfclk = v->dcfclkv_max0p9;

		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);



		context->watermarks.d.cstate_pstate.cstate_exit_ns =

		context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =

			v->stutter_exit_watermark * 1000;

		context->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =

		context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =

				v->stutter_enter_plus_exit_watermark * 1000;

		context->watermarks.d.cstate_pstate.pstate_change_ns =

		context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =

				v->dram_clock_change_watermark * 1000;

		context->watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

		context->watermarks.d.urgent_ns = v->urgent_watermark * 1000;

		context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

		context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;

	}



	v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
@@ -598,20 +598,20 @@ static void calc_wm_sets_and_perf_params( 
	v->dcfclk = v->dcfclk_per_state[v->voltage_level];

	dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);



	context->watermarks.a.cstate_pstate.cstate_exit_ns =

	context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =

		v->stutter_exit_watermark * 1000;

	context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

	context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

			v->stutter_enter_plus_exit_watermark * 1000;

	context->watermarks.a.cstate_pstate.pstate_change_ns =

	context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =

			v->dram_clock_change_watermark * 1000;

	context->watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

	context->watermarks.a.urgent_ns = v->urgent_watermark * 1000;

	context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

	context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;

	if (v->voltage_level >= 2) {

		context->watermarks.b = context->watermarks.a;

		context->watermarks.c = context->watermarks.a;

		context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;

		context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;

	}

	if (v->voltage_level >= 3)

		context->watermarks.d = context->watermarks.a;

		context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;

}



static bool dcn_bw_apply_registry_override(struct core_dc *dc)
@@ -916,17 +916,16 @@ bool dcn_validate_bandwidth( 


		display_pipe_configuration(v);

		calc_wm_sets_and_perf_params(context, v);

		context->fclk_khz = (int)(bw_consumed * 1000000 /

		context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /

				(ddr4_dram_factor_single_Channel * v->number_of_channels));

		context->dram_ccm_us = (int)(v->dram_clock_change_margin);

		context->min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);

		context->dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);

		context->dcfclk_khz = (int)(v->dcfclk * 1000);

		context->dispclk_khz = (int)(v->dispclk * 1000);

		context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin);

		context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);

		context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);

		context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);

		context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);

		if (dc->public.debug.max_disp_clk == true)

			context->dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);

		context->dppclk_khz = (int)(v->dppclk * 1000);

		context->dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;

			context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);

		context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;



		for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {

			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −19
Original line number Diff line number Diff line
@@ -970,13 +970,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) 
{

	int i;

	struct core_dc *core_dc = DC_TO_CORE(dc);

	struct validate_context *context = dm_alloc(sizeof(struct validate_context));



	if (!context) {

		dm_error("%s: failed to create validate ctx\n", __func__);

		return false;

	}

	dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);

	struct validate_context *context = core_dc->current_context;



	post_surface_trace(dc);
@@ -986,21 +980,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) 
			core_dc->hwss.power_down_front_end(

					core_dc, &context->res_ctx.pipe_ctx[i]);

		}

	if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {

		BREAK_TO_DEBUGGER();

		dc_resource_validate_ctx_destruct(context);

		dm_free(context);

		return false;

	}



	core_dc->hwss.set_bandwidth(core_dc, context, true);



	if (core_dc->current_context) {

		dc_resource_validate_ctx_destruct(core_dc->current_context);

		dm_free(core_dc->current_context);

	}

	core_dc->current_context = context;



	return true;

}

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

+3 −3
Original line number Diff line number Diff line
@@ -218,9 +218,9 @@ static void program_stutter_watermark(struct mem_input *mi, 
}



void dce_mem_input_program_display_marks(struct mem_input *mi,

	struct bw_watermarks nbp,

	struct bw_watermarks stutter,

	struct bw_watermarks urgent,

	struct dce_watermarks nbp,

	struct dce_watermarks stutter,

	struct dce_watermarks urgent,

	uint32_t total_dest_line_time_ns)

{

	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

+7 −5
Original line number Diff line number Diff line
@@ -25,6 +25,10 @@ 
#ifndef __DCE_MEM_INPUT_H__

#define __DCE_MEM_INPUT_H__



#include "dc_hw_types.h"

struct dce_watermarks;

struct mem_input;



#define MI_DCE_BASE_REG_LIST(id)\

	SRI(GRPH_ENABLE, DCP, id),\

	SRI(GRPH_CONTROL, DCP, id),\
@@ -262,8 +266,6 @@ struct dce_mem_input_wa { 
	uint8_t single_head_rdreq_dmif_limit;

};



struct mem_input;



void dce_mem_input_program_pte_vm(struct mem_input *mi,

	enum surface_pixel_format format,

	union dc_tiling_info *tiling_info,
@@ -288,9 +290,9 @@ void dce_mem_input_free_dmif(struct mem_input *mi, 
	uint32_t total_stream_num);



void dce_mem_input_program_display_marks(struct mem_input *mi,

	struct bw_watermarks nbp,

	struct bw_watermarks stutter,

	struct bw_watermarks urgent,

	struct dce_watermarks nbp,

	struct dce_watermarks stutter,

	struct dce_watermarks urgent,

	uint32_t total_dest_line_time_ns);



#endif /*__DCE_MEM_INPUT_H__*/