Commit 92039e8c authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

clk: qcom: dispcc-sm6350: Add CLK_OPS_PARENT_ENABLE to pixel&byte src 



Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to
ensure set_rate can succeed.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Fixes: 83751977 ("clk: qcom: Add display clock controller driver for  SM6350")
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221010155546.73884-1-konrad.dybcio@somainline.org
parent 6db4d77f

drivers/clk/qcom/dispcc-sm6350.c

+2 −2
Original line number Diff line number Diff line
@@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 
		.name = "disp_cc_mdss_pclk0_clk_src",

		.parent_data = disp_cc_parent_data_5,

		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),

		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,

		.ops = &clk_pixel_ops,

	},

};
@@ -385,7 +385,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { 
				&disp_cc_mdss_byte0_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,

			.ops = &clk_branch2_ops,

		},

	},