Commit 927e310e authored by Andre Przywara's avatar Andre Przywara Committed by Jernej Skrabec
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ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi 



The Allwinner T113-s SoC is apparently using the same (or at least a very
similar) die as the D1/D1s, but replaces the single RISC-V core with
two Arm Cortex-A7 cores.
Since the D1 core .dtsi already describes all common peripherals, we
just need a DT describing the ARM specific peripherals: the CPU cores,
the Generic Timer, the GIC and the PMU.
We include the core .dtsi directly from the riscv DT directory.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230320005249.13403-3-andre.przywara@arm.com


Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
parent a3eebcb6

arch/arm/boot/dts/sun8i-t113s.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)

// Copyright (C) 2022 Arm Ltd.



#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <riscv/allwinner/sunxi-d1s-t113.dtsi>

#include <riscv/allwinner/sunxi-d1-t113.dtsi>



/ {

	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <0>;

			clocks = <&ccu CLK_CPUX>;

			clock-names = "cpu";

		};



		cpu1: cpu@1 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

			clocks = <&ccu CLK_CPUX>;

			clock-names = "cpu";

		};

	};



	gic: interrupt-controller@1c81000 {

		compatible = "arm,gic-400";

		reg = <0x03021000 0x1000>,

		      <0x03022000 0x2000>,

		      <0x03024000 0x2000>,

		      <0x03026000 0x2000>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		interrupt-controller;

		#interrupt-cells = <3>;

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0>, <&cpu1>;

	};

};