Commit 92a34131 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g044: Add SSI support 



Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210814135526.15561-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6f48272f

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+76 −0
Original line number Diff line number Diff line
@@ -92,6 +92,82 @@ soc: soc { 
		#size-cells = <2>;

		ranges;



		ssi0: ssi@10049c00 {

			compatible = "renesas,r9a07g044-ssi",

				     "renesas,rz-ssi";

			reg = <0 0x10049c00 0 0x400>;

			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";

			clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,

				 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,

				 <&audio_clk1>, <&audio_clk2>;

			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";

			resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;

			power-domains = <&cpg>;

			#sound-dai-cells = <0>;

			status = "disabled";

		};



		ssi1: ssi@1004a000 {

			compatible = "renesas,r9a07g044-ssi",

				     "renesas,rz-ssi";

			reg = <0 0x1004a000 0 0x400>;

			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";

			clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,

				 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,

				 <&audio_clk1>, <&audio_clk2>;

			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";

			resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;

			power-domains = <&cpg>;

			#sound-dai-cells = <0>;

			status = "disabled";

		};



		ssi2: ssi@1004a400 {

			compatible = "renesas,r9a07g044-ssi",

				     "renesas,rz-ssi";

			reg = <0 0x1004a400 0 0x400>;

			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";

			clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,

				 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,

				 <&audio_clk1>, <&audio_clk2>;

			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";

			resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;

			power-domains = <&cpg>;

			#sound-dai-cells = <0>;

			status = "disabled";

		};



		ssi3: ssi@1004a800 {

			compatible = "renesas,r9a07g044-ssi",

				     "renesas,rz-ssi";

			reg = <0 0x1004a800 0 0x400>;

			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";

			clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,

				 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,

				 <&audio_clk1>, <&audio_clk2>;

			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";

			resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;

			power-domains = <&cpg>;

			#sound-dai-cells = <0>;

			status = "disabled";

		};



		scif0: serial@1004b800 {

			compatible = "renesas,scif-r9a07g044";

			reg = <0 0x1004b800 0 0x400>;