Commit 93266da2 authored by Uwe Kleine-König's avatar Uwe Kleine-König Committed by Rob Herring
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dt-bindings: display: Convert fsl,imx-fb.txt to dt-schema



Compared to the txt description this adds clocks and clock-names to
match reality.

Note that fsl,imx-lcdc was picked as the new name as this is the actual
hardware's name. There will be a new binding implementing the saner drm
concept that is supposed to supersede this legacy fb binding

Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221129180414.2729091-1-u.kleine-koenig@pengutronix.de


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 7621aabd
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Freescale imx21 Framebuffer

This framebuffer driver supports devices imx1, imx21, imx25, and imx27.

Required properties:
- compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
- reg : Should contain 1 register ranges(address and length)
- interrupts : One interrupt of the fb dev

Required nodes:
- display: Phandle to a display node as described in
	Documentation/devicetree/bindings/display/panel/display-timing.txt
	Additional, the display node has to define properties:
	- bits-per-pixel: Bits per pixel
	- fsl,pcr: LCDC PCR value
	A display node may optionally define
	- fsl,aus-mode: boolean to enable AUS mode (only for imx21)

Optional properties:
- lcd-supply: Regulator for LCD supply voltage.
- fsl,dmacr: DMA Control Register value. This is optional. By default, the
	register is not modified as recommended by the datasheet.
- fsl,lpccr: Contrast Control Register value. This property provides the
	default value for the contrast control register.
	If that property is omitted, the register is zeroed.
- fsl,lscr1: LCDC Sharp Configuration Register value.

Example:

	imxfb: fb@10021000 {
		compatible = "fsl,imx21-fb";
		interrupts = <61>;
		reg = <0x10021000 0x1000>;
		display = <&display0>;
	};

	...

	display0: display0 {
		model = "Primeview-PD050VL1";
		bits-per-pixel = <16>;
		fsl,pcr = <0xf0c88080>;	/* non-standard but required */
		display-timings {
			native-mode = <&timing_disp0>;
			timing_disp0: 640x480 {
				hactive = <640>;
				vactive = <480>;
				hback-porch = <112>;
				hfront-porch = <36>;
				hsync-len = <32>;
				vback-porch = <33>;
				vfront-porch = <33>;
				vsync-len = <2>;
				clock-frequency = <25000000>;
			};
		};
	};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX LCD Controller, found on i.MX1, i.MX21, i.MX25 and i.MX27

maintainers:
  - Sascha Hauer <s.hauer@pengutronix.de>
  - Pengutronix Kernel Team <kernel@pengutronix.de>

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx1-fb
          - fsl,imx21-fb
      - items:
          - enum:
              - fsl,imx25-fb
              - fsl,imx27-fb
          - const: fsl,imx21-fb

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: ipg
      - const: ahb
      - const: per

  display:
    $ref: /schemas/types.yaml#/definitions/phandle

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  lcd-supply:
    description:
      Regulator for LCD supply voltage.

  fsl,dmacr:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Override value for DMA Control Register

  fsl,lpccr:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Contrast Control Register value.

  fsl,lscr1:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      LCDC Sharp Configuration Register value.

required:
  - compatible
  - clocks
  - clock-names
  - display
  - interrupts
  - reg

additionalProperties: false

examples:
  - |
    imxfb: fb@10021000 {
        compatible = "fsl,imx21-fb";
        interrupts = <61>;
        reg = <0x10021000 0x1000>;
        display = <&display0>;
        clocks = <&clks 103>, <&clks 49>, <&clks 66>;
        clock-names = "ipg", "ahb", "per";
    };

    display0: display0 {
        model = "Primeview-PD050VL1";
        bits-per-pixel = <16>;
        fsl,pcr = <0xf0c88080>; /* non-standard but required */

        display-timings {
            native-mode = <&timing_disp0>;
            timing_disp0: timing0 {
                hactive = <640>;
                vactive = <480>;
                hback-porch = <112>;
                hfront-porch = <36>;
                hsync-len = <32>;
                vback-porch = <33>;
                vfront-porch = <33>;
                vsync-len = <2>;
                clock-frequency = <25000000>;
            };
        };
    };