Commit 936f9741 authored by kyrie wu's avatar kyrie wu Committed by Matthias Brugger
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arm64: dts: mt8195: add jpeg decode device node 



add mt8195 jpegdec device node

Signed-off-by: default avatarkyrie wu <kyrie.wu@mediatek.com>
Signed-off-by: default avatarirui wang <irui.wang@mediatek.com>
Link: https://lore.kernel.org/r/20230112084503.4277-3-irui.wang@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent a32a371f

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+60 −0
Original line number Diff line number Diff line
@@ -2305,6 +2305,66 @@ venc: video-codec@1a020000 { 
			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

		};



		jpgdec-master {

			compatible = "mediatek,mt8195-jpgdec";

			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;

			iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,

				 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,

				 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,

				 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,

				 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,

				 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;

			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			jpgdec@1a040000 {

				compatible = "mediatek,mt8195-jpgdec-hw";

				reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */

				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;

				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&vencsys CLK_VENC_JPGDEC>;

				clock-names = "jpgdec";

				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;

			};



			jpgdec@1a050000 {

				compatible = "mediatek,mt8195-jpgdec-hw";

				reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */

				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,

					 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;

				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&vencsys CLK_VENC_JPGDEC_C1>;

				clock-names = "jpgdec";

				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;

			};



			jpgdec@1b040000 {

				compatible = "mediatek,mt8195-jpgdec-hw";

				reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */

				iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,

					 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,

					 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,

					 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,

					 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,

					 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;

				interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;

				clock-names = "jpgdec";

				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;

			};

		};



		vencsys_core1: clock-controller@1b000000 {

			compatible = "mediatek,mt8195-vencsys_core1";

			reg = <0 0x1b000000 0 0x1000>;