Commit 939e4649 authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/hwcap: Add support for FEAT_RPRFM 



FEAT_RPRFM adds a new range prefetch hint within the existing PRFM space
for range prefetch hinting. Add a new hwcap to allow userspace to discover
support for the new instruction.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20221017152520.1039165-4-broonie@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b0ab73a5

Documentation/arm64/elf_hwcaps.rst

+3 −0
Original line number Diff line number Diff line
@@ -278,6 +278,9 @@ HWCAP2_SVE_EBF16 
HWCAP2_CSSC

    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.



HWCAP2_RPRFM

    Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ 
#define KERNEL_HWCAP_EBF16		__khwcap2_feature(EBF16)

#define KERNEL_HWCAP_SVE_EBF16		__khwcap2_feature(SVE_EBF16)

#define KERNEL_HWCAP_CSSC		__khwcap2_feature(CSSC)

#define KERNEL_HWCAP_RPRFM		__khwcap2_feature(RPRFM)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -94,5 +94,6 @@ 
#define HWCAP2_EBF16		(1UL << 32)

#define HWCAP2_SVE_EBF16	(1UL << 33)

#define HWCAP2_CSSC		(1UL << 34)

#define HWCAP2_RPRFM		(1UL << 35)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+2 −0
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 


static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),

		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
@@ -2817,6 +2818,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),

	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_RPRFM_IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),

#ifdef CONFIG_ARM64_SME

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -117,6 +117,7 @@ static const char *const hwcap_str[] = { 
	[KERNEL_HWCAP_EBF16]		= "ebf16",

	[KERNEL_HWCAP_SVE_EBF16]	= "sveebf16",

	[KERNEL_HWCAP_CSSC]		= "cssc",

	[KERNEL_HWCAP_RPRFM]		= "rprfm",

};



#ifdef CONFIG_COMPAT