Loading drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c +1 −1 Original line number Diff line number Diff line Loading @@ -70,7 +70,7 @@ static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy) HHI_MIPI_CNTL1_BANDGAP); regmap_write(priv->regmap, HHI_MIPI_CNTL2, FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) | FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x45a) | FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680)); reg = DSI_LANE_CLK; Loading drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +5 −5 Original line number Diff line number Diff line Loading @@ -237,11 +237,11 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, */ if (tmds_clk < 54 * MEGA) txposdiv = 8; else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA) else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA) txposdiv = 4; else if (tmds_clk >= 148.35 * MEGA && tmds_clk < 296.7 * MEGA) else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 * MEGA) txposdiv = 2; else if (tmds_clk >= 296.7 * MEGA && tmds_clk <= 594 * MEGA) else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA) txposdiv = 1; else return -EINVAL; Loading Loading @@ -324,12 +324,12 @@ static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw) clk_channel_bias = 0x34; /* 20mA */ impedance_en = 0xf; impedance = 0x36; /* 100ohm */ } else if (pixel_clk >= 74.175 * MEGA && pixel_clk <= 300 * MEGA) { } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) { data_channel_bias = 0x34; /* 20mA */ clk_channel_bias = 0x2c; /* 16mA */ impedance_en = 0xf; impedance = 0x36; /* 100ohm */ } else if (pixel_clk >= 27 * MEGA && pixel_clk < 74.175 * MEGA) { } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) { data_channel_bias = 0x14; /* 10mA */ clk_channel_bias = 0x14; /* 10mA */ impedance_en = 0x0; Loading drivers/phy/qualcomm/phy-qcom-qmp-combo.c +3 −2 Original line number Diff line number Diff line Loading @@ -2472,7 +2472,7 @@ static int qmp_combo_com_init(struct qmp_combo *qmp) ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); goto err_unlock; goto err_decrement_count; } ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); Loading Loading @@ -2522,7 +2522,8 @@ static int qmp_combo_com_init(struct qmp_combo *qmp) reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_unlock: err_decrement_count: qmp->init_count--; mutex_unlock(&qmp->phy_mutex); return ret; Loading drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +3 −2 Original line number Diff line number Diff line Loading @@ -379,7 +379,7 @@ static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy) ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); goto err_unlock; goto err_decrement_count; } ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); Loading Loading @@ -409,7 +409,8 @@ static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy) reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_unlock: err_decrement_count: qmp->init_count--; mutex_unlock(&qmp->phy_mutex); return ret; Loading drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +1 −1 Original line number Diff line number Diff line Loading @@ -115,11 +115,11 @@ struct phy_override_seq { * * @cfg_ahb_clk: AHB2PHY interface clock * @ref_clk: phy reference clock * @iface_clk: phy interface clock * @phy_reset: phy reset control * @vregs: regulator supplies bulk data * @phy_initialized: if PHY has been initialized correctly * @mode: contains the current mode the PHY is in * @update_seq_cfg: tuning parameters for phy init */ struct qcom_snps_hsphy { struct phy *phy; Loading Loading
drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c +1 −1 Original line number Diff line number Diff line Loading @@ -70,7 +70,7 @@ static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy) HHI_MIPI_CNTL1_BANDGAP); regmap_write(priv->regmap, HHI_MIPI_CNTL2, FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) | FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x45a) | FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680)); reg = DSI_LANE_CLK; Loading
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +5 −5 Original line number Diff line number Diff line Loading @@ -237,11 +237,11 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, */ if (tmds_clk < 54 * MEGA) txposdiv = 8; else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA) else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA) txposdiv = 4; else if (tmds_clk >= 148.35 * MEGA && tmds_clk < 296.7 * MEGA) else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 * MEGA) txposdiv = 2; else if (tmds_clk >= 296.7 * MEGA && tmds_clk <= 594 * MEGA) else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA) txposdiv = 1; else return -EINVAL; Loading Loading @@ -324,12 +324,12 @@ static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw) clk_channel_bias = 0x34; /* 20mA */ impedance_en = 0xf; impedance = 0x36; /* 100ohm */ } else if (pixel_clk >= 74.175 * MEGA && pixel_clk <= 300 * MEGA) { } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) { data_channel_bias = 0x34; /* 20mA */ clk_channel_bias = 0x2c; /* 16mA */ impedance_en = 0xf; impedance = 0x36; /* 100ohm */ } else if (pixel_clk >= 27 * MEGA && pixel_clk < 74.175 * MEGA) { } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) { data_channel_bias = 0x14; /* 10mA */ clk_channel_bias = 0x14; /* 10mA */ impedance_en = 0x0; Loading
drivers/phy/qualcomm/phy-qcom-qmp-combo.c +3 −2 Original line number Diff line number Diff line Loading @@ -2472,7 +2472,7 @@ static int qmp_combo_com_init(struct qmp_combo *qmp) ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); goto err_unlock; goto err_decrement_count; } ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); Loading Loading @@ -2522,7 +2522,8 @@ static int qmp_combo_com_init(struct qmp_combo *qmp) reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_unlock: err_decrement_count: qmp->init_count--; mutex_unlock(&qmp->phy_mutex); return ret; Loading
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +3 −2 Original line number Diff line number Diff line Loading @@ -379,7 +379,7 @@ static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy) ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); goto err_unlock; goto err_decrement_count; } ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); Loading Loading @@ -409,7 +409,8 @@ static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy) reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_unlock: err_decrement_count: qmp->init_count--; mutex_unlock(&qmp->phy_mutex); return ret; Loading
drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +1 −1 Original line number Diff line number Diff line Loading @@ -115,11 +115,11 @@ struct phy_override_seq { * * @cfg_ahb_clk: AHB2PHY interface clock * @ref_clk: phy reference clock * @iface_clk: phy interface clock * @phy_reset: phy reset control * @vregs: regulator supplies bulk data * @phy_initialized: if PHY has been initialized correctly * @mode: contains the current mode the PHY is in * @update_seq_cfg: tuning parameters for phy init */ struct qcom_snps_hsphy { struct phy *phy; Loading