Commit 9482a170 authored by Thierry Reding's avatar Thierry Reding
Browse files

ARM: tegra: Use proper tuple notation 



Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling to properly parse this data.

While at it, also remove the "immovable" bit from PCI addresses. All of
these addresses are in fact "movable".

Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent cc761754

arch/arm/boot/dts/tegra114.dtsi

+8 −6
Original line number Diff line number Diff line
@@ -255,14 +255,14 @@ gpio: gpio@6000d000 { 


	apbmisc@70000800 {

		compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64   /* Chip revision */

		       0x70000008 0x04>; /* Strapping options */

		reg = <0x70000800 0x64>, /* Chip revision */

		      <0x70000008 0x04>; /* Strapping options */

	};



	pinmux: pinmux@70000868 {

		compatible = "nvidia,tegra114-pinmux";

		reg = <0x70000868 0x148		/* Pad control registers */

		       0x70003000 0x40c>;	/* Mux registers */

		reg = <0x70000868 0x148>, /* Pad control registers */

		      <0x70003000 0x40c>; /* Mux registers */

	};



	/*
@@ -704,7 +704,8 @@ usb@7d000000 { 


	phy1: usb-phy@7d000000 {

		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";

		reg = <0x7d000000 0x4000 0x7d000000 0x4000>;

		reg = <0x7d000000 0x4000>,

		      <0x7d000000 0x4000>;

		phy_type = "utmi";

		clocks = <&tegra_car TEGRA114_CLK_USBD>,

			 <&tegra_car TEGRA114_CLK_PLL_U>,
@@ -741,7 +742,8 @@ usb@7d008000 { 


	phy3: usb-phy@7d008000 {

		compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";

		reg = <0x7d008000 0x4000 0x7d000000 0x4000>;

		reg = <0x7d008000 0x4000>,

		      <0x7d000000 0x4000>;

		phy_type = "utmi";

		clocks = <&tegra_car TEGRA114_CLK_USB3>,

			 <&tegra_car TEGRA114_CLK_PLL_U>,

arch/arm/boot/dts/tegra124.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -22,9 +22,9 @@ memory@80000000 { 
	pcie@1003000 {

		compatible = "nvidia,tegra124-pcie";

		device_type = "pci";

		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */

		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */

		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */

		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */

		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */

		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
@@ -38,11 +38,11 @@ pcie@1003000 { 
		#address-cells = <3>;

		#size-cells = <2>;



		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */

			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */

			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */

			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */

			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */

			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */

			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */

			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */

			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */



		clocks = <&tegra_car TEGRA124_CLK_PCIE>,

			 <&tegra_car TEGRA124_CLK_AFI>,
@@ -885,8 +885,8 @@ cec@70015000 { 


	soctherm: thermal-sensor@700e2000 {

		compatible = "nvidia,tegra124-soctherm";

		reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */

			0x0 0x60006000 0x0 0x400>; /* CAR reg_base */

		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */

		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */

		reg-names = "soctherm-reg", "car-reg";

		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,

arch/arm/boot/dts/tegra20.dtsi

+33 −31
Original line number Diff line number Diff line
@@ -174,8 +174,8 @@ timer@50040600 { 


	intc: interrupt-controller@50041000 {

		compatible = "arm,cortex-a9-gic";

		reg = <0x50041000 0x1000

		       0x50040100 0x0100>;

		reg = <0x50041000 0x1000>,

		      <0x50040100 0x0100>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;
@@ -274,15 +274,15 @@ gpio: gpio@6000d000 { 


	vde@6001a000 {

		compatible = "nvidia,tegra20-vde";

		reg = <0x6001a000 0x1000   /* Syntax Engine */

		       0x6001b000 0x1000   /* Video Bitstream Engine */

		       0x6001c000  0x100   /* Macroblock Engine */

		       0x6001c200  0x100   /* Post-processing Engine */

		       0x6001c400  0x100   /* Motion Compensation Engine */

		       0x6001c600  0x100   /* Transform Engine */

		       0x6001c800  0x100   /* Pixel prediction block */

		       0x6001ca00  0x100   /* Video DMA */

		       0x6001d800  0x300>; /* Video frame controls */

		reg = <0x6001a000 0x1000>, /* Syntax Engine */

		      <0x6001b000 0x1000>, /* Video Bitstream Engine */

		      <0x6001c000  0x100>, /* Macroblock Engine */

		      <0x6001c200  0x100>, /* Post-processing Engine */

		      <0x6001c400  0x100>, /* Motion Compensation Engine */

		      <0x6001c600  0x100>, /* Transform Engine */

		      <0x6001c800  0x100>, /* Pixel prediction block */

		      <0x6001ca00  0x100>, /* Video DMA */

		      <0x6001d800  0x300>; /* Video frame controls */

		reg-names = "sxe", "bsev", "mbe", "ppe", "mce",

			    "tfe", "ppb", "vdma", "frameid";

		iram = <&vde_pool>; /* IRAM region */
@@ -297,16 +297,16 @@ vde@6001a000 { 


	apbmisc@70000800 {

		compatible = "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64   /* Chip revision */

		       0x70000008 0x04>; /* Strapping options */

		reg = <0x70000800 0x64>, /* Chip revision */

		      <0x70000008 0x04>; /* Strapping options */

	};



	pinmux: pinmux@70000014 {

		compatible = "nvidia,tegra20-pinmux";

		reg = <0x70000014 0x10   /* Tri-state registers */

		       0x70000080 0x20   /* Mux registers */

		       0x700000a0 0x14   /* Pull-up/down registers */

		       0x70000868 0xa8>; /* Pad control registers */

		reg = <0x70000014 0x10>, /* Tri-state registers */

		      <0x70000080 0x20>, /* Mux registers */

		      <0x700000a0 0x14>, /* Pull-up/down registers */

		      <0x70000868 0xa8>; /* Pad control registers */

	};



	das@70000c00 {
@@ -621,8 +621,8 @@ tegra_pmc: pmc@7000e400 { 


	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra20-mc-gart";

		reg = <0x7000f000 0x400		/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

		reg = <0x7000f000 0x00000400>, /* controller registers */

		      <0x58000000 0x02000000>; /* GART aperture */

		clocks = <&tegra_car TEGRA20_CLK_MC>;

		clock-names = "mc";

		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@@ -651,12 +651,12 @@ fuse@7000f800 { 
	pcie@80003000 {

		compatible = "nvidia,tegra20-pcie";

		device_type = "pci";

		reg = <0x80003000 0x00000800   /* PADS registers */

		       0x80003800 0x00000200   /* AFI registers */

		       0x90000000 0x10000000>; /* configuration space */

		reg = <0x80003000 0x00000800>, /* PADS registers */

		      <0x80003800 0x00000200>, /* AFI registers */

		      <0x90000000 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */

			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupt-names = "intr", "msi";



		#interrupt-cells = <1>;
@@ -667,11 +667,11 @@ pcie@80003000 { 
		#address-cells = <3>;

		#size-cells = <2>;



		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */

			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */

			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */

			  0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */

		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */

			 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */

			 <0x01000000 0 0          0x82000000 0 0x00010000>, /* downstream I/O */

			 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */

			 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */



		clocks = <&tegra_car TEGRA20_CLK_PEX>,

			 <&tegra_car TEGRA20_CLK_AFI>,
@@ -728,7 +728,8 @@ usb@c5000000 { 


	phy1: usb-phy@c5000000 {

		compatible = "nvidia,tegra20-usb-phy";

		reg = <0xc5000000 0x4000 0xc5000000 0x4000>;

		reg = <0xc5000000 0x4000>,

		      <0xc5000000 0x4000>;

		phy_type = "utmi";

		clocks = <&tegra_car TEGRA20_CLK_USBD>,

			 <&tegra_car TEGRA20_CLK_PLL_U>,
@@ -790,7 +791,8 @@ usb@c5008000 { 


	phy3: usb-phy@c5008000 {

		compatible = "nvidia,tegra20-usb-phy";

		reg = <0xc5008000 0x4000 0xc5000000 0x4000>;

		reg = <0xc5008000 0x4000>,

		      <0xc5000000 0x4000>;

		phy_type = "utmi";

		clocks = <&tegra_car TEGRA20_CLK_USB3>,

			 <&tegra_car TEGRA20_CLK_PLL_U>,

arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts

+2 −2
Original line number Diff line number Diff line
@@ -248,8 +248,8 @@ reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { 
		regulator-max-microvolt = <3300000>;

		regulator-type = "voltage";

		gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;

		states = <1800000 0x0

			  3300000 0x1>;

		states = <1800000 0x0>,

			 <3300000 0x1>;

		startup-delay-us = <100000>;

		vin-supply = <&vddio_sdmmc_1v8_reg>;

	};

arch/arm/boot/dts/tegra30.dtsi

+36 −33
Original line number Diff line number Diff line
@@ -20,12 +20,12 @@ memory@80000000 { 
	pcie@3000 {

		compatible = "nvidia,tegra30-pcie";

		device_type = "pci";

		reg = <0x00003000 0x00000800   /* PADS registers */

		       0x00003800 0x00000200   /* AFI registers */

		       0x10000000 0x10000000>; /* configuration space */

		reg = <0x00003000 0x00000800>, /* PADS registers */

		      <0x00003800 0x00000200>, /* AFI registers */

		      <0x10000000 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */

			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupt-names = "intr", "msi";



		#interrupt-cells = <1>;
@@ -36,12 +36,12 @@ pcie@3000 { 
		#address-cells = <3>;

		#size-cells = <2>;



		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */

			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */

			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */

			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */

			  0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */

		ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */

			 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */

			 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */

			 <0x01000000 0 0          0x02000000 0 0x00010000>, /* downstream I/O */

			 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */

			 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */



		clocks = <&tegra_car TEGRA30_CLK_PCIE>,

			 <&tegra_car TEGRA30_CLK_AFI>,
@@ -185,8 +185,8 @@ gr2d@54140000 { 
		gr3d@54180000 {

			compatible = "nvidia,tegra30-gr3d";

			reg = <0x54180000 0x00040000>;

			clocks = <&tegra_car TEGRA30_CLK_GR3D

				  &tegra_car TEGRA30_CLK_GR3D2>;

			clocks = <&tegra_car TEGRA30_CLK_GR3D>,

				 <&tegra_car TEGRA30_CLK_GR3D2>;

			clock-names = "3d", "3d2";

			resets = <&tegra_car 24>,

				 <&tegra_car 98>;
@@ -275,8 +275,8 @@ timer@50040600 { 


	intc: interrupt-controller@50041000 {

		compatible = "arm,cortex-a9-gic";

		reg = <0x50041000 0x1000

		       0x50040100 0x0100>;

		reg = <0x50041000 0x1000>,

		      <0x50040100 0x0100>;

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;
@@ -406,15 +406,15 @@ gpio: gpio@6000d000 { 


	vde@6001a000 {

		compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";

		reg = <0x6001a000 0x1000   /* Syntax Engine */

		       0x6001b000 0x1000   /* Video Bitstream Engine */

		       0x6001c000  0x100   /* Macroblock Engine */

		       0x6001c200  0x100   /* Post-processing Engine */

		       0x6001c400  0x100   /* Motion Compensation Engine */

		       0x6001c600  0x100   /* Transform Engine */

		       0x6001c800  0x100   /* Pixel prediction block */

		       0x6001ca00  0x100   /* Video DMA */

		       0x6001d800  0x400>; /* Video frame controls */

		reg = <0x6001a000 0x1000>, /* Syntax Engine */

		      <0x6001b000 0x1000>, /* Video Bitstream Engine */

		      <0x6001c000  0x100>, /* Macroblock Engine */

		      <0x6001c200  0x100>, /* Post-processing Engine */

		      <0x6001c400  0x100>, /* Motion Compensation Engine */

		      <0x6001c600  0x100>, /* Transform Engine */

		      <0x6001c800  0x100>, /* Pixel prediction block */

		      <0x6001ca00  0x100>, /* Video DMA */

		      <0x6001d800  0x400>; /* Video frame controls */

		reg-names = "sxe", "bsev", "mbe", "ppe", "mce",

			    "tfe", "ppb", "vdma", "frameid";

		iram = <&vde_pool>; /* IRAM region */
@@ -430,14 +430,14 @@ vde@6001a000 { 


	apbmisc@70000800 {

		compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64   /* Chip revision */

		       0x70000008 0x04>; /* Strapping options */

		reg = <0x70000800 0x64>, /* Chip revision */

		      <0x70000008 0x04>; /* Strapping options */

	};



	pinmux: pinmux@70000868 {

		compatible = "nvidia,tegra30-pinmux";

		reg = <0x70000868 0xd4    /* Pad control registers */

		       0x70003000 0x3e4>; /* Mux registers */

		reg = <0x70000868 0x0d4>, /* Pad control registers */

		      <0x70003000 0x3e4>; /* Mux registers */

	};



	/*
@@ -772,8 +772,8 @@ hda@70030000 { 


	ahub@70080000 {

		compatible = "nvidia,tegra30-ahub";

		reg = <0x70080000 0x200

		       0x70080200 0x100>;

		reg = <0x70080000 0x200>,

		      <0x70080200 0x100>;

		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,

			 <&tegra_car TEGRA30_CLK_APBIF>;
@@ -908,7 +908,8 @@ usb@7d000000 { 


	phy1: usb-phy@7d000000 {

		compatible = "nvidia,tegra30-usb-phy";

		reg = <0x7d000000 0x4000 0x7d000000 0x4000>;

		reg = <0x7d000000 0x4000>,

		      <0x7d000000 0x4000>;

		phy_type = "utmi";

		clocks = <&tegra_car TEGRA30_CLK_USBD>,

			 <&tegra_car TEGRA30_CLK_PLL_U>,
@@ -946,7 +947,8 @@ usb@7d004000 { 


	phy2: usb-phy@7d004000 {

		compatible = "nvidia,tegra30-usb-phy";

		reg = <0x7d004000 0x4000 0x7d000000 0x4000>;

		reg = <0x7d004000 0x4000>,

		      <0x7d000000 0x4000>;

		phy_type = "utmi";

		clocks = <&tegra_car TEGRA30_CLK_USB2>,

			 <&tegra_car TEGRA30_CLK_PLL_U>,
@@ -983,7 +985,8 @@ usb@7d008000 { 


	phy3: usb-phy@7d008000 {

		compatible = "nvidia,tegra30-usb-phy";

		reg = <0x7d008000 0x4000 0x7d000000 0x4000>;

		reg = <0x7d008000 0x4000>,

		      <0x7d000000 0x4000>;

		phy_type = "utmi";

		clocks = <&tegra_car TEGRA30_CLK_USB3>,

			 <&tegra_car TEGRA30_CLK_PLL_U>,