Commit 94a70c87 authored by Stephan Gerhold's avatar Stephan Gerhold Committed by Bjorn Andersson
Browse files

clk: qcom: smd-rpm: Add clocks for MSM8909 



MSM8909 has mostly the same as clocks in RPM as MSM8916,
but additionally the QPIC clock for the NAND flash controller.

Signed-off-by: default avatarStephan Gerhold <stephan.gerhold@kernkonzept.com>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220706134132.3623415-7-stephan.gerhold@kernkonzept.com
parent 1727a402

drivers/clk/qcom/clk-smd-rpm.c

+36 −1
Original line number Diff line number Diff line
@@ -417,6 +417,7 @@ DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 
DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);

DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);

DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000);

DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000);
@@ -427,6 +428,40 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 192 
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000);



static struct clk_smd_rpm *msm8909_clks[] = {

	[RPM_SMD_PCNOC_CLK]		= &msm8916_pcnoc_clk,

	[RPM_SMD_PCNOC_A_CLK]		= &msm8916_pcnoc_a_clk,

	[RPM_SMD_SNOC_CLK]		= &msm8916_snoc_clk,

	[RPM_SMD_SNOC_A_CLK]		= &msm8916_snoc_a_clk,

	[RPM_SMD_BIMC_CLK]		= &msm8916_bimc_clk,

	[RPM_SMD_BIMC_A_CLK]		= &msm8916_bimc_a_clk,

	[RPM_SMD_QPIC_CLK]		= &qcs404_qpic_clk,

	[RPM_SMD_QPIC_CLK_A]		= &qcs404_qpic_a_clk,

	[RPM_SMD_QDSS_CLK]		= &msm8916_qdss_clk,

	[RPM_SMD_QDSS_A_CLK]		= &msm8916_qdss_a_clk,

	[RPM_SMD_BB_CLK1]		= &msm8916_bb_clk1,

	[RPM_SMD_BB_CLK1_A]		= &msm8916_bb_clk1_a,

	[RPM_SMD_BB_CLK2]		= &msm8916_bb_clk2,

	[RPM_SMD_BB_CLK2_A]		= &msm8916_bb_clk2_a,

	[RPM_SMD_RF_CLK1]		= &msm8916_rf_clk1,

	[RPM_SMD_RF_CLK1_A]		= &msm8916_rf_clk1_a,

	[RPM_SMD_RF_CLK2]		= &msm8916_rf_clk2,

	[RPM_SMD_RF_CLK2_A]		= &msm8916_rf_clk2_a,

	[RPM_SMD_BB_CLK1_PIN]		= &msm8916_bb_clk1_pin,

	[RPM_SMD_BB_CLK1_A_PIN]		= &msm8916_bb_clk1_a_pin,

	[RPM_SMD_BB_CLK2_PIN]		= &msm8916_bb_clk2_pin,

	[RPM_SMD_BB_CLK2_A_PIN]		= &msm8916_bb_clk2_a_pin,

	[RPM_SMD_RF_CLK1_PIN]		= &msm8916_rf_clk1_pin,

	[RPM_SMD_RF_CLK1_A_PIN]		= &msm8916_rf_clk1_a_pin,

	[RPM_SMD_RF_CLK2_PIN]		= &msm8916_rf_clk2_pin,

	[RPM_SMD_RF_CLK2_A_PIN]		= &msm8916_rf_clk2_a_pin,

};



static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {

	.clks = msm8909_clks,

	.num_clks = ARRAY_SIZE(msm8909_clks),

};



static struct clk_smd_rpm *msm8916_clks[] = {

	[RPM_SMD_PCNOC_CLK]		= &msm8916_pcnoc_clk,

	[RPM_SMD_PCNOC_A_CLK]		= &msm8916_pcnoc_a_clk,
@@ -787,7 +822,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { 
};



DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);

DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000);



static struct clk_smd_rpm *qcs404_clks[] = {
@@ -1146,6 +1180,7 @@ static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { 
static const struct of_device_id rpm_smd_clk_match_table[] = {

	{ .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },

	{ .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },

	{ .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },

	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },

	{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },

	{ .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },