Commit 94fb0ef4 authored by Vince Bridgers's avatar Vince Bridgers Committed by David S. Miller
Browse files

Altera TSE: Add Altera Ethernet Driver MSGDMA File Components 



This patch adds the MSGDMA soft IP support for the Altera Triple
Speed Ethernet driver.

Signed-off-by: default avatarVince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 04add4ab

drivers/net/ethernet/altera/altera_msgdma.c

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Original line number Diff line number Diff line 
/* Altera TSE SGDMA and MSGDMA Linux driver

 * Copyright (C) 2014 Altera Corporation. All rights reserved

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/netdevice.h>

#include "altera_utils.h"

#include "altera_tse.h"

#include "altera_msgdmahw.h"



/* No initialization work to do for MSGDMA */

int msgdma_initialize(struct altera_tse_private *priv)

{

	return 0;

}



void msgdma_uninitialize(struct altera_tse_private *priv)

{

}



void msgdma_reset(struct altera_tse_private *priv)

{

	int counter;

	struct msgdma_csr *txcsr =

		(struct msgdma_csr *)priv->tx_dma_csr;

	struct msgdma_csr *rxcsr =

		(struct msgdma_csr *)priv->rx_dma_csr;



	/* Reset Rx mSGDMA */

	iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);

	iowrite32(MSGDMA_CSR_CTL_RESET, &rxcsr->control);



	counter = 0;

	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {

		if (tse_bit_is_clear(&rxcsr->status,

				     MSGDMA_CSR_STAT_RESETTING))

			break;

		udelay(1);

	}



	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)

		netif_warn(priv, drv, priv->dev,

			   "TSE Rx mSGDMA resetting bit never cleared!\n");



	/* clear all status bits */

	iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);



	/* Reset Tx mSGDMA */

	iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);

	iowrite32(MSGDMA_CSR_CTL_RESET, &txcsr->control);



	counter = 0;

	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {

		if (tse_bit_is_clear(&txcsr->status,

				     MSGDMA_CSR_STAT_RESETTING))

			break;

		udelay(1);

	}



	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)

		netif_warn(priv, drv, priv->dev,

			   "TSE Tx mSGDMA resetting bit never cleared!\n");



	/* clear all status bits */

	iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);

}



void msgdma_disable_rxirq(struct altera_tse_private *priv)

{

	struct msgdma_csr *csr = priv->rx_dma_csr;

	tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);

}



void msgdma_enable_rxirq(struct altera_tse_private *priv)

{

	struct msgdma_csr *csr = priv->rx_dma_csr;

	tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);

}



void msgdma_disable_txirq(struct altera_tse_private *priv)

{

	struct msgdma_csr *csr = priv->tx_dma_csr;

	tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);

}



void msgdma_enable_txirq(struct altera_tse_private *priv)

{

	struct msgdma_csr *csr = priv->tx_dma_csr;

	tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);

}



void msgdma_clear_rxirq(struct altera_tse_private *priv)

{

	struct msgdma_csr *csr = priv->rx_dma_csr;

	iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);

}



void msgdma_clear_txirq(struct altera_tse_private *priv)

{

	struct msgdma_csr *csr = priv->tx_dma_csr;

	iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);

}



/* return 0 to indicate transmit is pending */

int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)

{

	struct msgdma_extended_desc *desc = priv->tx_dma_desc;



	iowrite32(lower_32_bits(buffer->dma_addr), &desc->read_addr_lo);

	iowrite32(upper_32_bits(buffer->dma_addr), &desc->read_addr_hi);

	iowrite32(0, &desc->write_addr_lo);

	iowrite32(0, &desc->write_addr_hi);

	iowrite32(buffer->len, &desc->len);

	iowrite32(0, &desc->burst_seq_num);

	iowrite32(MSGDMA_DESC_TX_STRIDE, &desc->stride);

	iowrite32(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);

	return 0;

}



u32 msgdma_tx_completions(struct altera_tse_private *priv)

{

	u32 ready = 0;

	u32 inuse;

	u32 status;

	struct msgdma_csr *txcsr =

		(struct msgdma_csr *)priv->tx_dma_csr;



	/* Get number of sent descriptors */

	inuse = ioread32(&txcsr->rw_fill_level) & 0xffff;



	if (inuse) { /* Tx FIFO is not empty */

		ready = priv->tx_prod - priv->tx_cons - inuse - 1;

	} else {

		/* Check for buffered last packet */

		status = ioread32(&txcsr->status);

		if (status & MSGDMA_CSR_STAT_BUSY)

			ready = priv->tx_prod - priv->tx_cons - 1;

		else

			ready = priv->tx_prod - priv->tx_cons;

	}

	return ready;

}



/* Put buffer to the mSGDMA RX FIFO

 */

int msgdma_add_rx_desc(struct altera_tse_private *priv,

			struct tse_buffer *rxbuffer)

{

	struct msgdma_extended_desc *desc = priv->rx_dma_desc;

	u32 len = priv->rx_dma_buf_sz;

	dma_addr_t dma_addr = rxbuffer->dma_addr;

	u32 control = (MSGDMA_DESC_CTL_END_ON_EOP

			| MSGDMA_DESC_CTL_END_ON_LEN

			| MSGDMA_DESC_CTL_TR_COMP_IRQ

			| MSGDMA_DESC_CTL_EARLY_IRQ

			| MSGDMA_DESC_CTL_TR_ERR_IRQ

			| MSGDMA_DESC_CTL_GO);



	iowrite32(0, &desc->read_addr_lo);

	iowrite32(0, &desc->read_addr_hi);

	iowrite32(lower_32_bits(dma_addr), &desc->write_addr_lo);

	iowrite32(upper_32_bits(dma_addr), &desc->write_addr_hi);

	iowrite32(len, &desc->len);

	iowrite32(0, &desc->burst_seq_num);

	iowrite32(0x00010001, &desc->stride);

	iowrite32(control, &desc->control);

	return 1;

}



/* status is returned on upper 16 bits,

 * length is returned in lower 16 bits

 */

u32 msgdma_rx_status(struct altera_tse_private *priv)

{

	u32 rxstatus = 0;

	u32 pktlength;

	u32 pktstatus;

	struct msgdma_csr *rxcsr =

		(struct msgdma_csr *)priv->rx_dma_csr;

	struct msgdma_response *rxresp =

		(struct msgdma_response *)priv->rx_dma_resp;



	if (ioread32(&rxcsr->resp_fill_level) & 0xffff) {

		pktlength = ioread32(&rxresp->bytes_transferred);

		pktstatus = ioread32(&rxresp->status);

		rxstatus = pktstatus;

		rxstatus = rxstatus << 16;

		rxstatus |= (pktlength & 0xffff);

	}

	return rxstatus;

}

drivers/net/ethernet/altera/altera_msgdma.h

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Original line number Diff line number Diff line 
/* Altera TSE SGDMA and MSGDMA Linux driver

 * Copyright (C) 2014 Altera Corporation. All rights reserved

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef __ALTERA_MSGDMA_H__

#define __ALTERA_MSGDMA_H__



void msgdma_reset(struct altera_tse_private *);

void msgdma_enable_txirq(struct altera_tse_private *);

void msgdma_enable_rxirq(struct altera_tse_private *);

void msgdma_disable_rxirq(struct altera_tse_private *);

void msgdma_disable_txirq(struct altera_tse_private *);

void msgdma_clear_rxirq(struct altera_tse_private *);

void msgdma_clear_txirq(struct altera_tse_private *);

u32 msgdma_tx_completions(struct altera_tse_private *);

int msgdma_add_rx_desc(struct altera_tse_private *, struct tse_buffer *);

int msgdma_tx_buffer(struct altera_tse_private *, struct tse_buffer *);

u32 msgdma_rx_status(struct altera_tse_private *);

int msgdma_initialize(struct altera_tse_private *);

void msgdma_uninitialize(struct altera_tse_private *);



#endif /*  __ALTERA_MSGDMA_H__ */

drivers/net/ethernet/altera/altera_msgdmahw.h

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Original line number Diff line number Diff line 
/* Altera TSE SGDMA and MSGDMA Linux driver

 * Copyright (C) 2014 Altera Corporation. All rights reserved

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef __ALTERA_MSGDMAHW_H__

#define __ALTERA_MSGDMAHW_H__



/* mSGDMA standard descriptor format

 */

struct msgdma_desc {

	u32 read_addr;	/* data buffer source address */

	u32 write_addr;	/* data buffer destination address */

	u32 len;	/* the number of bytes to transfer per descriptor */

	u32 control;	/* characteristics of the transfer */

};



/* mSGDMA extended descriptor format

 */

struct msgdma_extended_desc {

	u32 read_addr_lo;	/* data buffer source address low bits */

	u32 write_addr_lo;	/* data buffer destination address low bits */

	u32 len;		/* the number of bytes to transfer

				 * per descriptor

				 */

	u32 burst_seq_num;	/* bit 31:24 write burst

				 * bit 23:16 read burst

				 * bit 15:0  sequence number

				 */

	u32 stride;		/* bit 31:16 write stride

				 * bit 15:0  read stride

				 */

	u32 read_addr_hi;	/* data buffer source address high bits */

	u32 write_addr_hi;	/* data buffer destination address high bits */

	u32 control;		/* characteristics of the transfer */

};



/* mSGDMA descriptor control field bit definitions

 */

#define MSGDMA_DESC_CTL_SET_CH(x)	((x) & 0xff)

#define MSGDMA_DESC_CTL_GEN_SOP		BIT(8)

#define MSGDMA_DESC_CTL_GEN_EOP		BIT(9)

#define MSGDMA_DESC_CTL_PARK_READS	BIT(10)

#define MSGDMA_DESC_CTL_PARK_WRITES	BIT(11)

#define MSGDMA_DESC_CTL_END_ON_EOP	BIT(12)

#define MSGDMA_DESC_CTL_END_ON_LEN	BIT(13)

#define MSGDMA_DESC_CTL_TR_COMP_IRQ	BIT(14)

#define MSGDMA_DESC_CTL_EARLY_IRQ	BIT(15)

#define MSGDMA_DESC_CTL_TR_ERR_IRQ	(0xff << 16)

#define MSGDMA_DESC_CTL_EARLY_DONE	BIT(24)

/* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the

 * descriptor FIFO(s)

 */

#define MSGDMA_DESC_CTL_GO		BIT(31)



/* Tx buffer control flags

 */

#define MSGDMA_DESC_CTL_TX_FIRST	(MSGDMA_DESC_CTL_GEN_SOP |	\

					 MSGDMA_DESC_CTL_TR_ERR_IRQ |	\

					 MSGDMA_DESC_CTL_GO)



#define MSGDMA_DESC_CTL_TX_MIDDLE	(MSGDMA_DESC_CTL_TR_ERR_IRQ |	\

					 MSGDMA_DESC_CTL_GO)



#define MSGDMA_DESC_CTL_TX_LAST		(MSGDMA_DESC_CTL_GEN_EOP |	\

					 MSGDMA_DESC_CTL_TR_COMP_IRQ |	\

					 MSGDMA_DESC_CTL_TR_ERR_IRQ |	\

					 MSGDMA_DESC_CTL_GO)



#define MSGDMA_DESC_CTL_TX_SINGLE	(MSGDMA_DESC_CTL_GEN_SOP |	\

					 MSGDMA_DESC_CTL_GEN_EOP |	\

					 MSGDMA_DESC_CTL_TR_COMP_IRQ |	\

					 MSGDMA_DESC_CTL_TR_ERR_IRQ |	\

					 MSGDMA_DESC_CTL_GO)



#define MSGDMA_DESC_CTL_RX_SINGLE	(MSGDMA_DESC_CTL_END_ON_EOP |	\

					 MSGDMA_DESC_CTL_END_ON_LEN |	\

					 MSGDMA_DESC_CTL_TR_COMP_IRQ |	\

					 MSGDMA_DESC_CTL_EARLY_IRQ |	\

					 MSGDMA_DESC_CTL_TR_ERR_IRQ |	\

					 MSGDMA_DESC_CTL_GO)



/* mSGDMA extended descriptor stride definitions

 */

#define MSGDMA_DESC_TX_STRIDE		(0x00010001)

#define MSGDMA_DESC_RX_STRIDE		(0x00010001)



/* mSGDMA dispatcher control and status register map

 */

struct msgdma_csr {

	u32 status;		/* Read/Clear */

	u32 control;		/* Read/Write */

	u32 rw_fill_level;	/* bit 31:16 - write fill level

				 * bit 15:0  - read fill level

				 */

	u32 resp_fill_level;	/* bit 15:0 */

	u32 rw_seq_num;		/* bit 31:16 - write sequence number

				 * bit 15:0  - read sequence number

				 */

	u32 pad[3];		/* reserved */

};



/* mSGDMA CSR status register bit definitions

 */

#define MSGDMA_CSR_STAT_BUSY			BIT(0)

#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY		BIT(1)

#define MSGDMA_CSR_STAT_DESC_BUF_FULL		BIT(2)

#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY		BIT(3)

#define MSGDMA_CSR_STAT_RESP_BUF_FULL		BIT(4)

#define MSGDMA_CSR_STAT_STOPPED			BIT(5)

#define MSGDMA_CSR_STAT_RESETTING		BIT(6)

#define MSGDMA_CSR_STAT_STOPPED_ON_ERR		BIT(7)

#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY	BIT(8)

#define MSGDMA_CSR_STAT_IRQ			BIT(9)

#define MSGDMA_CSR_STAT_MASK			0x3FF

#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ	0x1FF



#define MSGDMA_CSR_STAT_BUSY_GET(v)			GET_BIT_VALUE(v, 0)

#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v)		GET_BIT_VALUE(v, 1)

#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v)		GET_BIT_VALUE(v, 2)

#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v)		GET_BIT_VALUE(v, 3)

#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v)		GET_BIT_VALUE(v, 4)

#define MSGDMA_CSR_STAT_STOPPED_GET(v)			GET_BIT_VALUE(v, 5)

#define MSGDMA_CSR_STAT_RESETTING_GET(v)		GET_BIT_VALUE(v, 6)

#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v)		GET_BIT_VALUE(v, 7)

#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v)		GET_BIT_VALUE(v, 8)

#define MSGDMA_CSR_STAT_IRQ_GET(v)			GET_BIT_VALUE(v, 9)



/* mSGDMA CSR control register bit definitions

 */

#define MSGDMA_CSR_CTL_STOP			BIT(0)

#define MSGDMA_CSR_CTL_RESET			BIT(1)

#define MSGDMA_CSR_CTL_STOP_ON_ERR		BIT(2)

#define MSGDMA_CSR_CTL_STOP_ON_EARLY		BIT(3)

#define MSGDMA_CSR_CTL_GLOBAL_INTR		BIT(4)

#define MSGDMA_CSR_CTL_STOP_DESCS		BIT(5)



/* mSGDMA CSR fill level bits

 */

#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v)		(((v) & 0xffff0000) >> 16)

#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v)		((v) & 0x0000ffff)

#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v)	((v) & 0x0000ffff)



/* mSGDMA response register map

 */

struct msgdma_response {

	u32 bytes_transferred;

	u32 status;

};



/* mSGDMA response register bit definitions

 */

#define MSGDMA_RESP_EARLY_TERM	BIT(8)

#define MSGDMA_RESP_ERR_MASK	0xFF



#endif /* __ALTERA_MSGDMA_H__*/