Loading drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +9 −0 Original line number Diff line number Diff line Loading @@ -184,6 +184,15 @@ static int nvkm_fifo_init(struct nvkm_engine *engine) { struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nvkm_runq *runq; u32 mask = 0; if (fifo->func->init_pbdmas) { nvkm_runq_foreach(runq, fifo) mask |= BIT(runq->id); fifo->func->init_pbdmas(fifo, mask); } fifo->func->init(fifo); Loading drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +15 −7 Original line number Diff line number Diff line Loading @@ -627,18 +627,16 @@ gf100_fifo_fini(struct nvkm_fifo *base) } static void gf100_fifo_init(struct nvkm_fifo *base) gf100_fifo_init_pbdmas(struct nvkm_fifo *fifo, u32 mask) { struct gf100_fifo *fifo = gf100_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; int i; struct nvkm_device *device = fifo->engine.subdev.device; /* Enable PBDMAs. */ nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); nvkm_wr32(device, 0x002204, (1 << fifo->pbdma_nr) - 1); nvkm_wr32(device, 0x000204, mask); nvkm_wr32(device, 0x002204, mask); /* Assign engines to PBDMAs. */ if (fifo->pbdma_nr >= 3) { if ((mask & 7) == 7) { nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ Loading @@ -647,6 +645,15 @@ gf100_fifo_init(struct nvkm_fifo *base) nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ } } static void gf100_fifo_init(struct nvkm_fifo *base) { struct gf100_fifo *fifo = gf100_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; int i; /* PBDMA[n] */ for (i = 0; i < fifo->pbdma_nr; i++) { nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); Loading Loading @@ -756,6 +763,7 @@ gf100_fifo = { .runq_nr = gf100_fifo_runq_nr, .runl_ctor = gf100_fifo_runl_ctor, .init = gf100_fifo_init, .init_pbdmas = gf100_fifo_init_pbdmas, .fini = gf100_fifo_fini, .intr = gf100_fifo_intr, .mmu_fault = &gf100_fifo_mmu_fault, Loading drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +9 −11 Original line number Diff line number Diff line Loading @@ -278,16 +278,8 @@ static const struct nvkm_runl_func gk104_runl = { }; void gk104_fifo_pbdma_init(struct gk104_fifo *fifo) { struct nvkm_device *device = fifo->base.engine.subdev.device; nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); } const struct gk104_fifo_pbdma_func gk104_fifo_pbdma = { .init = gk104_fifo_pbdma_init, }; int Loading Loading @@ -962,6 +954,14 @@ gk104_fifo_fini(struct nvkm_fifo *base) flush_work(&fifo->recover.work); } void gk104_fifo_init_pbdmas(struct nvkm_fifo *fifo, u32 mask) { struct nvkm_device *device = fifo->engine.subdev.device; nvkm_wr32(device, 0x000204, mask); } void gk104_fifo_init(struct nvkm_fifo *base) { Loading @@ -969,9 +969,6 @@ gk104_fifo_init(struct nvkm_fifo *base) struct nvkm_device *device = fifo->base.engine.subdev.device; int i; /* Enable PBDMAs. */ fifo->func->pbdma->init(fifo); /* PBDMA[n] */ for (i = 0; i < fifo->pbdma_nr; i++) { nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); Loading Loading @@ -1147,6 +1144,7 @@ gk104_fifo = { .runq_nr = gf100_fifo_runq_nr, .runl_ctor = gk104_fifo_runl_ctor, .init = gk104_fifo_init, .init_pbdmas = gk104_fifo_init_pbdmas, .fini = gk104_fifo_fini, .intr = gk104_fifo_intr, .intr_mmu_fault_unit = gf100_fifo_intr_mmu_fault_unit, Loading drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +0 −1 Original line number Diff line number Diff line Loading @@ -75,7 +75,6 @@ void gk104_fifo_init(struct nvkm_fifo *base); void gk104_fifo_fini(struct nvkm_fifo *base); extern const struct gk104_fifo_pbdma_func gk104_fifo_pbdma; void gk104_fifo_pbdma_init(struct gk104_fifo *); extern const struct nvkm_enum gk104_fifo_fault_access[]; extern const struct nvkm_enum gk104_fifo_fault_engine[]; extern const struct nvkm_enum gk104_fifo_fault_reason[]; Loading drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c +1 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,7 @@ gk110_fifo = { .runq_nr = gf100_fifo_runq_nr, .runl_ctor = gk104_fifo_runl_ctor, .init = gk104_fifo_init, .init_pbdmas = gk104_fifo_init_pbdmas, .fini = gk104_fifo_fini, .intr = gk104_fifo_intr, .intr_mmu_fault_unit = gf100_fifo_intr_mmu_fault_unit, Loading Loading
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +9 −0 Original line number Diff line number Diff line Loading @@ -184,6 +184,15 @@ static int nvkm_fifo_init(struct nvkm_engine *engine) { struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nvkm_runq *runq; u32 mask = 0; if (fifo->func->init_pbdmas) { nvkm_runq_foreach(runq, fifo) mask |= BIT(runq->id); fifo->func->init_pbdmas(fifo, mask); } fifo->func->init(fifo); Loading
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +15 −7 Original line number Diff line number Diff line Loading @@ -627,18 +627,16 @@ gf100_fifo_fini(struct nvkm_fifo *base) } static void gf100_fifo_init(struct nvkm_fifo *base) gf100_fifo_init_pbdmas(struct nvkm_fifo *fifo, u32 mask) { struct gf100_fifo *fifo = gf100_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; int i; struct nvkm_device *device = fifo->engine.subdev.device; /* Enable PBDMAs. */ nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); nvkm_wr32(device, 0x002204, (1 << fifo->pbdma_nr) - 1); nvkm_wr32(device, 0x000204, mask); nvkm_wr32(device, 0x002204, mask); /* Assign engines to PBDMAs. */ if (fifo->pbdma_nr >= 3) { if ((mask & 7) == 7) { nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ Loading @@ -647,6 +645,15 @@ gf100_fifo_init(struct nvkm_fifo *base) nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ } } static void gf100_fifo_init(struct nvkm_fifo *base) { struct gf100_fifo *fifo = gf100_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; int i; /* PBDMA[n] */ for (i = 0; i < fifo->pbdma_nr; i++) { nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); Loading Loading @@ -756,6 +763,7 @@ gf100_fifo = { .runq_nr = gf100_fifo_runq_nr, .runl_ctor = gf100_fifo_runl_ctor, .init = gf100_fifo_init, .init_pbdmas = gf100_fifo_init_pbdmas, .fini = gf100_fifo_fini, .intr = gf100_fifo_intr, .mmu_fault = &gf100_fifo_mmu_fault, Loading
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +9 −11 Original line number Diff line number Diff line Loading @@ -278,16 +278,8 @@ static const struct nvkm_runl_func gk104_runl = { }; void gk104_fifo_pbdma_init(struct gk104_fifo *fifo) { struct nvkm_device *device = fifo->base.engine.subdev.device; nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); } const struct gk104_fifo_pbdma_func gk104_fifo_pbdma = { .init = gk104_fifo_pbdma_init, }; int Loading Loading @@ -962,6 +954,14 @@ gk104_fifo_fini(struct nvkm_fifo *base) flush_work(&fifo->recover.work); } void gk104_fifo_init_pbdmas(struct nvkm_fifo *fifo, u32 mask) { struct nvkm_device *device = fifo->engine.subdev.device; nvkm_wr32(device, 0x000204, mask); } void gk104_fifo_init(struct nvkm_fifo *base) { Loading @@ -969,9 +969,6 @@ gk104_fifo_init(struct nvkm_fifo *base) struct nvkm_device *device = fifo->base.engine.subdev.device; int i; /* Enable PBDMAs. */ fifo->func->pbdma->init(fifo); /* PBDMA[n] */ for (i = 0; i < fifo->pbdma_nr; i++) { nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); Loading Loading @@ -1147,6 +1144,7 @@ gk104_fifo = { .runq_nr = gf100_fifo_runq_nr, .runl_ctor = gk104_fifo_runl_ctor, .init = gk104_fifo_init, .init_pbdmas = gk104_fifo_init_pbdmas, .fini = gk104_fifo_fini, .intr = gk104_fifo_intr, .intr_mmu_fault_unit = gf100_fifo_intr_mmu_fault_unit, Loading
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +0 −1 Original line number Diff line number Diff line Loading @@ -75,7 +75,6 @@ void gk104_fifo_init(struct nvkm_fifo *base); void gk104_fifo_fini(struct nvkm_fifo *base); extern const struct gk104_fifo_pbdma_func gk104_fifo_pbdma; void gk104_fifo_pbdma_init(struct gk104_fifo *); extern const struct nvkm_enum gk104_fifo_fault_access[]; extern const struct nvkm_enum gk104_fifo_fault_engine[]; extern const struct nvkm_enum gk104_fifo_fault_reason[]; Loading
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c +1 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,7 @@ gk110_fifo = { .runq_nr = gf100_fifo_runq_nr, .runl_ctor = gk104_fifo_runl_ctor, .init = gk104_fifo_init, .init_pbdmas = gk104_fifo_init_pbdmas, .fini = gk104_fifo_fini, .intr = gk104_fifo_intr, .intr_mmu_fault_unit = gf100_fifo_intr_mmu_fault_unit, Loading