Commit 98806c08 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Add sierraforest 

Add v1.00 from:
https://github.com/intel/perfmon/pull/69



Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230413132949.3487664-4-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent dbe9d887

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ GenuineIntel-6-1[AEF],v3,nehalemep,core 
GenuineIntel-6-2E,v3,nehalemex,core

GenuineIntel-6-2A,v19,sandybridge,core

GenuineIntel-6-(8F|CF),v1.12,sapphirerapids,core

GenuineIntel-6-AF,v1.00,sierraforest,core

GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core

GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core

GenuineIntel-6-55-[01234],v1.29,skylakex,core

tools/perf/pmu-events/arch/x86/sierraforest/cache.json

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+155 −0
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[

    {

        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",

        "SampleAfterValue": "200003",

        "UMask": "0x41"

    },

    {

        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",

        "SampleAfterValue": "200003",

        "UMask": "0x4f"

    },

    {

        "BriefDescription": "Counts the number of load ops retired.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x81"

    },

    {

        "BriefDescription": "Counts the number of store ops retired.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x82"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x400",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x800",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x6"

    }

]

tools/perf/pmu-events/arch/x86/sierraforest/frontend.json

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+16 −0
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[

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "SampleAfterValue": "200003",

        "UMask": "0x3"

    },

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    }

]

tools/perf/pmu-events/arch/x86/sierraforest/memory.json

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+20 −0
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[

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    }

]

tools/perf/pmu-events/arch/x86/sierraforest/other.json

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[

    {

        "BriefDescription": "Counts demand data reads that have any type of response.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    }

]