Commit 98e95e4f authored by Josip Pavic's avatar Josip Pavic Committed by Alex Deucher
Browse files

drm/amd/display: log additional register state for debug 



[Why & How]
Extend existing state collection functions to add some additional
registers useful for debug, and add state collection function for DC
hubbub

Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarJosip Pavic <Josip.Pavic@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 97b9c006

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

+17 −1
Original line number Diff line number Diff line
@@ -121,6 +121,10 @@ struct dcn_hubbub_registers { 
	uint32_t DCN_VM_AGP_BASE;

	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;

	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;

	uint32_t DCN_VM_FAULT_ADDR_MSB;

	uint32_t DCN_VM_FAULT_ADDR_LSB;

	uint32_t DCN_VM_FAULT_CNTL;

	uint32_t DCN_VM_FAULT_STATUS;

	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;

	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;

	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
@@ -233,7 +237,19 @@ struct dcn_hubbub_registers { 
		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\

		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\

		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\

		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB

		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\

		type DCN_VM_FAULT_ADDR_MSB;\

		type DCN_VM_FAULT_ADDR_LSB;\

		type DCN_VM_ERROR_STATUS_CLEAR;\

		type DCN_VM_ERROR_STATUS_MODE;\

		type DCN_VM_ERROR_INTERRUPT_ENABLE;\

		type DCN_VM_RANGE_FAULT_DISABLE;\

		type DCN_VM_PRQ_FAULT_DISABLE;\

		type DCN_VM_ERROR_STATUS;\

		type DCN_VM_ERROR_VMID;\

		type DCN_VM_ERROR_TABLE_LEVEL;\

		type DCN_VM_ERROR_PIPE;\

		type DCN_VM_ERROR_INTERRUPT_STATUS



#define HUBBUB_STUTTER_REG_FIELD_LIST(type) \

		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

+29 −0
Original line number Diff line number Diff line
@@ -871,6 +871,8 @@ void hubp1_read_state_common(struct hubp *hubp) 
	struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;

	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;

	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;

	uint32_t aperture_low_msb, aperture_low_lsb;

	uint32_t aperture_high_msb, aperture_high_lsb;



	/* Requester */

	REG_GET(HUBPRET_CONTROL,
@@ -881,6 +883,22 @@ void hubp1_read_state_common(struct hubp *hubp) 
			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,

			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);



	REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB,

			MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb);



	REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB,

			MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb);



	REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB,

			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb);



	REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB,

			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb);



	// On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format

	rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6);

	rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6);



	/* DLG - Per hubp */

	REG_GET_2(BLANK_OFFSET_0,

		REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
@@ -1037,6 +1055,17 @@ void hubp1_read_state_common(struct hubp *hubp) 
			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,

			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);



	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,

			PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);



	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,

			PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);



	REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,

			PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);



	REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,

			PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);

}



void hubp1_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h

+4 −0
Original line number Diff line number Diff line
@@ -682,6 +682,10 @@ struct dcn_hubp_state { 
	uint32_t min_ttu_vblank;

	uint32_t qos_level_low_wm;

	uint32_t qos_level_high_wm;

	uint32_t primary_surface_addr_lo;

	uint32_t primary_surface_addr_hi;

	uint32_t primary_meta_addr_lo;

	uint32_t primary_meta_addr_hi;

};



struct dcn10_hubp {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+6 −0
Original line number Diff line number Diff line
@@ -1388,6 +1388,12 @@ void optc1_read_otg_state(struct optc *optc1, 


	REG_GET(OPTC_INPUT_GLOBAL_CONTROL,

			OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);



	REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,

			OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);



	REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,

			OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);

}



bool optc1_get_otg_active_size(struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

+2 −0
Original line number Diff line number Diff line
@@ -578,6 +578,8 @@ struct dcn_otg_state { 
	uint32_t underflow_occurred_status;

	uint32_t otg_enabled;

	uint32_t blank_enabled;

	uint32_t vertical_interrupt2_en;

	uint32_t vertical_interrupt2_line;

};



void optc1_read_otg_state(struct optc *optc1,