Commit 9956b94e authored by Stephan Gerhold's avatar Stephan Gerhold Committed by Linus Walleij
Browse files

ARM: dts: ux500: Remove unused ste-href-ab8505.dtsi



The pin configuration for HREF boards with AB8505 was added in
commit 77ad9dfc ("ARM: ux500: move last AB8505 set-up to DT").
As the commit message notes, it was unused back then and it has
remained so even today, especially considering AB8505 did not have
proper device tree support until recently.

We are now preparing to add support for some Samsung smartphones
that are using AB8505. However, they use different pin configs
because using ste-href-ab8505.dtsi is known to break UART.
There were not many HREFs with AB8505, so at this point it seems
unlikely that we will ever make use of this include. Remove it.

Signed-off-by: default avatarStephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191219202052.19039-2-stephan@gerhold.net


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 42a1e945
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2014 Linaro Ltd.
 */

/ {
	soc {
		prcmu@80157000 {
			ab8505 {
				ab8505-gpio {
					/* Hog a few default settings */
					pinctrl-names = "default";
					pinctrl-0 = <&gpio2_default_mode>,
						    <&gpio10_default_mode>,
						    <&gpio11_default_mode>,
						    <&gpio13_default_mode>,
						    <&gpio34_default_mode>,
						    <&gpio50_default_mode>,
						    <&pwm_default_mode>,
						    <&adi2_default_mode>,
						    <&modsclsda_default_mode>,
						    <&resethw_default_mode>,
						    <&service_default_mode>;

					/*
					 * Pins 2, 10, 11, 13, 34 and 50
					 * are muxed in as GPIO, and configured as INPUT PULL DOWN
					 */
					gpio2 {
						gpio2_default_mode: gpio2_default {
							default_mux {
								function = "gpio";
								groups = "gpio2_a_1";
							};
							default_cfg {
								pins = "GPIO2_R5";
								input-enable;
								bias-pull-down;
							};
						};
					};
					gpio10 {
						gpio10_default_mode: gpio10_default {
							default_mux {
								function = "gpio";
								groups = "gpio10_d_1";
							};
							default_cfg {
								pins = "GPIO10_B16";
								input-enable;
								bias-pull-down;
							};
						};
					};
					gpio11 {
						gpio11_default_mode: gpio11_default {
							default_mux {
								function = "gpio";
								groups = "gpio11_d_1";
							};
							default_cfg {
								pins = "GPIO11_B17";
								input-enable;
								bias-pull-down;
							};
						};
					};
					gpio13 {
						gpio13_default_mode: gpio13_default {
							default_mux {
								function = "gpio";
								groups = "gpio13_d_1";
							};
							default_cfg {
								pins = "GPIO13_D17";
								input-enable;
								bias-disable;
							};
						};
					};
					gpio34 {
						gpio34_default_mode: gpio34_default {
							default_mux {
								function = "gpio";
								groups = "gpio34_a_1";
							};
							default_cfg {
								pins = "GPIO34_H14";
								input-enable;
								bias-pull-down;
							};
						};
					};
					gpio50 {
						gpio50_default_mode: gpio50_default {
							default_mux {
								function = "gpio";
								groups = "gpio50_d_1";
							};
							default_cfg {
								pins = "GPIO50_L4";
								input-enable;
								bias-disable;
							};
						};
					};
					/* This sets up the PWM pin 14 */
					pwm {
						pwm_default_mode: pwm_default {
							default_mux {
								function = "pwmout";
								groups = "pwmout1_d_1";
							};
							default_cfg {
								pins = "GPIO14_C16";
								input-enable;
								bias-pull-down;
							};
						};
					};
					/* This sets up audio interface 2 */
					adi2 {
						adi2_default_mode: adi2_default {
							default_mux {
								function = "adi2";
								groups = "adi2_d_1";
							};
							default_cfg {
								pins = "GPIO17_P2",
									 "GPIO18_N3",
									 "GPIO19_T1",
									 "GPIO20_P3";
								input-enable;
								bias-pull-down;
							};
						};
					};
					/* Modem I2C setup (SCL and SDA pins) */
					modsclsda {
						modsclsda_default_mode: modsclsda_default {
							default_mux {
								function = "modsclsda";
								groups = "modsclsda_d_1";
							};
							default_cfg {
								pins = "GPIO40_J15",
									"GPIO41_J14";
								input-enable;
								bias-pull-down;
							};
						};
					};
					resethw {
						resethw_default_mode: resethw_default {
							default_mux {
								function = "resethw";
								groups = "resethw_d_1";
							};
							default_cfg {
								pins = "GPIO52_D16";
								input-enable;
								bias-pull-down;
							};
						};
					};
					service {
						service_default_mode: service_default {
							default_mux {
								function = "service";
								groups = "service_d_1";
							};
							default_cfg {
								pins = "GPIO53_D15";
								input-enable;
								bias-pull-down;
							};
						};
					};
					/*
					 * Clock output pins associated with regulators.
					 */
					sysclkreq2 {
						sysclkreq2_default_mode: sysclkreq2_default {
							default_mux {
								function = "sysclkreq";
								groups = "sysclkreq2_d_1";
							};
							default_cfg {
								pins = "GPIO1_N4";
								input-enable;
								bias-disable;
							};
						};
						sysclkreq2_sleep_mode: sysclkreq2_sleep {
							default_mux {
								function = "gpio";
								groups = "gpio1_a_1";
							};
							default_cfg {
								pins = "GPIO1_N4";
								input-enable;
								bias-pull-down;
							};
						};
					};
					sysclkreq4 {
						sysclkreq4_default_mode: sysclkreq4_default {
							default_mux {
								function = "sysclkreq";
								groups = "sysclkreq4_d_1";
							};
							default_cfg {
								pins = "GPIO3_P5";
								input-enable;
								bias-disable;
							};
						};
						sysclkreq4_sleep_mode: sysclkreq4_sleep {
							default_mux {
								function = "gpio";
								groups = "gpio3_a_1";
							};
							default_cfg {
								pins = "GPIO3_P5";
								input-enable;
								bias-pull-down;
							};
						};
					};
				};
			};
		};
	};
};