Commit 9a8b3036 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Fix uncore topics for skylake 



Move events from 'uncore-other' topic classification to cache and
interconnect.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230413132949.3487664-19-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent f58468a8

tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json

+14 −14
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",

        "UMask": "0x86",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
@@ -15,7 +15,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",

        "UMask": "0x88",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
@@ -24,7 +24,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",

        "UMask": "0x81",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
@@ -33,7 +33,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",

        "UMask": "0x8f",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
@@ -42,7 +42,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",

        "UMask": "0x16",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
@@ -51,7 +51,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",

        "UMask": "0x18",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
@@ -60,7 +60,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",

        "UMask": "0x1f",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
@@ -69,7 +69,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",

        "UMask": "0x26",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
@@ -78,7 +78,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",

        "UMask": "0x21",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
@@ -87,7 +87,7 @@ 
        "PerPkg": "1",

        "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",

        "UMask": "0x2f",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
@@ -95,7 +95,7 @@ 
        "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",

        "PerPkg": "1",

        "UMask": "0x48",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
@@ -103,7 +103,7 @@ 
        "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",

        "PerPkg": "1",

        "UMask": "0x44",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
@@ -111,7 +111,7 @@ 
        "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",

        "PerPkg": "1",

        "UMask": "0x81",

        "Unit": "CBO"

        "Unit": "CBOX"

    },

    {

        "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
@@ -119,6 +119,6 @@ 
        "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",

        "PerPkg": "1",

        "UMask": "0x41",

        "Unit": "CBO"

        "Unit": "CBOX"

    }

]

tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json

0 → 100644
+67 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",

        "EventCode": "0x84",

        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",

        "EventCode": "0x80",

        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

        "CounterMask": "1",

        "EventCode": "0x80",

        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",

        "EventCode": "0x80",

        "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",

        "PerPkg": "1",

        "UMask": "0x2",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",

        "PerPkg": "1",

        "UMask": "0x2",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",

        "PerPkg": "1",

        "UMask": "0x2",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",

        "PerPkg": "1",

        "UMask": "0x20",

        "Unit": "ARB"

    }

]

tools/perf/pmu-events/arch/x86/skylake/uncore-other.json

+0 −65
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",

        "EventCode": "0x84",

        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",

        "EventCode": "0x80",

        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

        "CounterMask": "1",

        "EventCode": "0x80",

        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",

        "EventCode": "0x80",

        "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",

        "PerPkg": "1",

        "UMask": "0x2",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",

        "PerPkg": "1",

        "UMask": "0x1",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",

        "PerPkg": "1",

        "UMask": "0x2",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",

        "PerPkg": "1",

        "UMask": "0x2",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",

        "EventCode": "0x81",

        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",

        "PerPkg": "1",

        "UMask": "0x20",

        "Unit": "ARB"

    },

    {

        "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",

        "EventCode": "0xff",