Merge tag 'qcom-pinctrl-6.2-2' of...

Qualcomm Technologies, Inc. IPQ8074 TLMM block

This binding describes the Top Level Mode Multiplexer block found in the

IPQ8074 platform.

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,ipq8074-pinctrl"

- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: the base address and size of the TLMM register space.

- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: should specify the TLMM summary IRQ.

- interrupt-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as an interrupt controller

- #interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/interrupt-controller/irq.h>

- gpio-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as a gpio controller

- #gpio-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/gpio/gpio.h>

- gpio-ranges:

	Usage: required

	Definition:  see ../gpio/gpio.txt

- gpio-reserved-ranges:

	Usage: optional

	Definition: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

- pins:

	Usage: required

	Value type: <string-array>

	Definition: List of gpio pins affected by the properties specified in

		    this subnode.  Valid pins are:

		    gpio0-gpio69

- function:

	Usage: required

	Value type: <string>

	Definition: Specify the alternative function to be configured for the

		    specified pins. Functions are only valid for gpio pins.

		    Valid values are:

		    atest_char, atest_char0, atest_char1, atest_char2,

		    atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,

		    audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,

		    audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,

		    blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,

		    blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,

		    blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,

		    blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,

		    blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1,

		    cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en,

		    ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0,

		    mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc,

		    mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk,

		    pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync,

		    pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1,

		    pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,

		    qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,

		    qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,

		    qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,

		    qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,

		    qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,

		    qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b,

		    qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a,

		    wci2b, wci2c, wci2d

- bias-disable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as no pull.

- bias-pull-down:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as pull down.

- bias-pull-up:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as pull up.

- output-high:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    high.

- output-low:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    low.

- drive-strength:

	Usage: optional

	Value type: <u32>

	Definition: Selects the drive strength for the specified pins, in mA.

		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16

Example:

	tlmm: pinctrl@1000000 {

		compatible = "qcom,ipq8074-pinctrl";

		reg = <0x1000000 0x300000>;

		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-ranges = <&tlmm 0 0 70>;

		interrupt-controller;

		#interrupt-cells = <2>;

		uart2: uart2-default {

			mux {

				pins = "gpio23", "gpio24";

				function = "blsp4_uart1";

			};

			rx {

				pins = "gpio23";

				drive-strength = <4>;

				bias-disable;

			};

			tx {

				pins = "gpio24";

				drive-strength = <2>;

				bias-pull-up;

			};

		};

	};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ8074 TLMM pin controller

maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:

  Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.

properties:

  compatible:

    const: qcom,ipq8074-pinctrl

  reg:

    maxItems: 1

  interrupts: true

  interrupt-controller: true

  "#interrupt-cells": true

  gpio-controller: true

  "#gpio-cells": true

  gpio-ranges: true

  wakeup-parent: true

  gpio-reserved-ranges:

    minItems: 1

    maxItems: 35

  gpio-line-names:

    maxItems: 70

patternProperties:

  "-state$":

    oneOf:

      - $ref: "#/$defs/qcom-ipq8074-tlmm-state"

      - patternProperties:

          "-pins$":

            $ref: "#/$defs/qcom-ipq8074-tlmm-state"

        additionalProperties: false

$defs:

  qcom-ipq8074-tlmm-state:

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          pattern: "^gpio([0-9]|[1-6][0-9]|70)$"

        minItems: 1

        maxItems: 36

      function:

        description:

          Specify the alternative function to be configured for the specified

          pins.

        enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,

                atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,

                audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,

                audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,

                blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,

                blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,

                blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,

                blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,

                blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0,

                cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0,

                led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2,

                mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,

                pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx,

                pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0,

                pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,

                qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,

                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,

                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,

                qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,

                qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,

                qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,

                tsens_max, wci2a, wci2b, wci2c, wci2d ]

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      drive-strength: true

      input-enable: true

      output-high: true

      output-low: true

    required:

      - pins

    additionalProperties: false

allOf:

  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:

  - compatible

  - reg

additionalProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@1000000 {

        compatible = "qcom,ipq8074-pinctrl";

        reg = <0x01000000 0x300000>;

        gpio-controller;

        #gpio-cells = <0x2>;

        gpio-ranges = <&tlmm 0 0 70>;

        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <0x2>;

        serial4-state {

            pins = "gpio23", "gpio24";

            function = "blsp4_uart1";

            drive-strength = <8>;

            bias-disable;

        };

    };

Qualcomm MSM8660 TLMM block

Required properties:

- compatible: "qcom,msm8660-pinctrl"

- reg: Should be the base address and length of the TLMM block.

- interrupts: Should be the parent IRQ of the TLMM block.

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells: Should be two.

- gpio-controller: Marks the device node as a GPIO controller.

- #gpio-cells : Should be two.

                The first cell is the gpio pin number and the

                second cell is used for optional parameters.

- gpio-ranges: see ../gpio/gpio.txt

Optional properties:

- gpio-reserved-ranges: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

Qualcomm's pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,

 output-low, output-high.

Non-empty subnodes must specify the 'pins' property.

Valid values for pins are:

  gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data

Valid values for function are:

  gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b,

  gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n,

  gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,

  gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,

  gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,

  lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,

  usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs

Example:

	msmgpio: pinctrl@800000 {

		compatible = "qcom,msm8660-pinctrl";

		reg = <0x800000 0x4000>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-ranges = <&msmgpio 0 0 173>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <0 16 0x4>;

		pinctrl-names = "default";

		pinctrl-0 = <&gsbi12_uart>;

		gsbi12_uart: gsbi12-uart {

			mux {

				pins = "gpio117", "gpio118";

				function = "gsbi12";

			};

			tx {

				pins = "gpio118";

				drive-strength = <8>;

				bias-disable;

			};

			rx {

				pins = "gpio117";

				drive-strength = <2>;

				bias-pull-up;

			};

		};

	};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8660 TLMM pin controller

maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:

  Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC.

properties:

  compatible:

    const: qcom,msm8660-pinctrl

  reg:

    maxItems: 1

  interrupts: true

  interrupt-controller: true

  "#interrupt-cells": true

  gpio-controller: true

  "#gpio-cells": true

  gpio-ranges: true

  wakeup-parent: true

  gpio-reserved-ranges:

    minItems: 1

    maxItems: 86

  gpio-line-names:

    maxItems: 173

patternProperties:

  "-state$":

    oneOf:

      - $ref: "#/$defs/qcom-msm8660-tlmm-state"

      - patternProperties:

          "-pins$":

            $ref: "#/$defs/qcom-msm8660-tlmm-state"

        additionalProperties: false

$defs:

  qcom-msm8660-tlmm-state:

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          oneOf:

            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-2])$"

            - enum: [ sdc3_clk, sdc3_cmd, sdc3_data, sdc4_clk, sdc4_cmd, sdc4_data ]

        minItems: 1

        maxItems: 36

      function:

        description:

          Specify the alternative function to be configured for the specified

          pins.

        enum: [ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a,

                gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n,

                gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2,

                gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, gsbi2_spi_cs3_n, gsbi3,

                gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4,

                gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12,

                hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2,

                sdc5, tsif1, tsif2, usb_fs1, usb_fs1_oe_n, usb_fs2,

                usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs ]

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      drive-strength: true

      input-enable: true

      output-high: true

      output-low: true

    required:

      - pins

    additionalProperties: false

allOf:

  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:

  - compatible

  - reg

additionalProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@800000 {

        compatible = "qcom,msm8660-pinctrl";

        reg = <0x800000 0x4000>;

        gpio-controller;

        gpio-ranges = <&tlmm 0 0 173>;

        #gpio-cells = <2>;

        interrupts = <0 16 0x4>;

        interrupt-controller;

        #interrupt-cells = <2>;

        gsbi3-i2c-state {

            pins = "gpio43", "gpio44";

            function = "gsbi3";

            drive-strength = <8>;

            bias-disable;

        };

    };

Qualcomm MSM8916 TLMM block

This binding describes the Top Level Mode Multiplexer block found in the

MSM8916 platform.

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,msm8916-pinctrl"

- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: the base address and size of the TLMM register space.

- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: should specify the TLMM summary IRQ.

- interrupt-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as an interrupt controller

- #interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/interrupt-controller/irq.h>

- gpio-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as a gpio controller

- #gpio-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/gpio/gpio.h>

- gpio-ranges:

	Usage: required

	Definition:  see ../gpio/gpio.txt

- gpio-reserved-ranges:

	Usage: optional

	Definition: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

- pins:

	Usage: required

	Value type: <string-array>

	Definition: List of gpio pins affected by the properties specified in

		    this subnode.  Valid pins are:

		    gpio0-gpio121,

		    sdc1_clk,

		    sdc1_cmd,

		    sdc1_data

		    sdc2_clk,

		    sdc2_cmd,

		    sdc2_data,

		    qdsd_cmd,

		    qdsd_data0,

		    qdsd_data1,

		    qdsd_data2,

		    qdsd_data3

- function:

	Usage: required

	Value type: <string>

	Definition: Specify the alternative function to be configured for the

		    specified pins. Functions are only valid for gpio pins.

		    Valid values are:

	adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,

	atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0,

	atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en,

	bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,

	blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2,

	blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3,

	blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4,

	blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2,

	cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c,

	cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out,

	display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us,

	ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,

	gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, gsm0_tx1,

	gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, ldo_en,

	ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, nav_pps, nav_tsync,

	pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc,

	pwr_crypto_enabled_a, pwr_crypto_enabled_b, pwr_modem_enabled_a,

	pwr_modem_enabled_b, pwr_nav_enabled_a, pwr_nav_enabled_b,

	qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, qdss_ctitrig_in_b0,

	qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, qdss_ctitrig_out_a1,

	qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, qdss_traceclk_a,

	qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,

	qdss_tracedata_b, reset_n, sd_card, sd_write, sec_mi2s, smb_int,

	ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm,

	wcss_wlan, webcam1_rst

- bias-disable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as no pull.

- bias-pull-down:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as pull down.

- bias-pull-up:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as pull up.

- output-high:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    high.

		    Not valid for sdc pins.

- output-low:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    low.

		    Not valid for sdc pins.

- drive-strength:

	Usage: optional

	Value type: <u32>

	Definition: Selects the drive strength for the specified pins, in mA.

		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16

Example:

	tlmm: pinctrl@1000000 {

		compatible = "qcom,msm8916-pinctrl";

		reg = <0x1000000 0x300000>;

		interrupts = <0 208 0>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-ranges = <&tlmm 0 0 122>;

		interrupt-controller;

		#interrupt-cells = <2>;

		uart2: uart2-default {

			mux {

				pins = "gpio4", "gpio5";

				function = "blsp_uart2";

			};

			tx {

				pins = "gpio4";

				drive-strength = <4>;

				bias-disable;

			};

			rx {

				pins = "gpio5";

				drive-strength = <2>;

				bias-pull-up;

			};

		};

	};