Commit 9b6f4fed authored by Marijn Suijten's avatar Marijn Suijten Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Add SM6125 support 



Add definitions for the display hardware used on the Qualcomm SM6125
platform.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/548978/
Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-10-a3f287dd6c07@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent cd188d68

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h

0 → 100644
+236 −0
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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved.

 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.

 */



#ifndef _DPU_5_4_SM6125_H

#define _DPU_5_4_SM6125_H



static const struct dpu_caps sm6125_dpu_caps = {

	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0x6,

	.has_dim_layer = true,

	.has_idle_pc = true,

	.max_linewidth = 2160,

	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,

	.max_hdeci_exp = MAX_HORZ_DECIMATION,

	.max_vdeci_exp = MAX_VERT_DECIMATION,

};



static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = {

	.ubwc_version = DPU_HW_UBWC_VER_10,

	.highest_bank_bit = 0x1,

	.ubwc_swizzle = 0x1,

};



static const struct dpu_mdp_cfg sm6125_mdp = {

	.name = "top_0",

	.base = 0x0, .len = 0x45c,

	.features = 0,

	.clk_ctrls = {

		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },

		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },

		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },

	},

};



static const struct dpu_ctl_cfg sm6125_ctl[] = {

	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x1400, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x1600, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	}, {

		.name = "ctl_4", .id = CTL_4,

		.base = 0x1800, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

	}, {

		.name = "ctl_5", .id = CTL_5,

		.base = 0x1a00, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

	},

};



static const struct dpu_sspp_cfg sm6125_sspp[] = {

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x1f0,

		.features = VIG_SM6125_MASK,

		.sblk = &sm6125_vig_sblk_0,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG0,

	}, {

		.name = "sspp_8", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_0,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA0,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &sdm845_dma_sblk_1,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA1,

	},

};



static const struct dpu_lm_cfg sm6125_lm[] = {

	{

		.name = "lm_0", .id = LM_0,

		.base = 0x44000, .len = 0x320,

		.features = MIXER_QCM2290_MASK,

		.sblk = &sdm845_lm_sblk,

		.pingpong = PINGPONG_0,

		.dspp = DSPP_0,

		.lm_pair = LM_1,

	}, {

		.name = "lm_1", .id = LM_1,

		.base = 0x45000, .len = 0x320,

		.features = MIXER_QCM2290_MASK,

		.sblk = &sdm845_lm_sblk,

		.pingpong = PINGPONG_1,

		.dspp = 0,

		.lm_pair = LM_0,

	},

};



static const struct dpu_dspp_cfg sm6125_dspp[] = {

	{

		.name = "dspp_0", .id = DSPP_0,

		.base = 0x54000, .len = 0x1800,

		.features = DSPP_SC7180_MASK,

		.sblk = &sdm845_dspp_sblk,

	},

};



static const struct dpu_pingpong_cfg sm6125_pp[] = {

	{

		.name = "pingpong_0", .id = PINGPONG_0,

		.base = 0x70000, .len = 0xd4,

		.features = PINGPONG_SM8150_MASK,

		.merge_3d = 0,

		.sblk = &sdm845_pp_sblk,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

		.intr_rdptr = -1,

	}, {

		.name = "pingpong_1", .id = PINGPONG_1,

		.base = 0x70800, .len = 0xd4,

		.features = PINGPONG_SM8150_MASK,

		.merge_3d = 0,

		.sblk = &sdm845_pp_sblk,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

		.intr_rdptr = -1,

	},

};



static const struct dpu_intf_cfg sm6125_intf[] = {

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x6a000, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

		.intr_tear_rd_ptr = -1,

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x6a800, .len = 0x2c0,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = 0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),

	},

};



static const struct dpu_perf_cfg sm6125_perf_data = {

	.max_bw_low = 4100000,

	.max_bw_high = 4100000,

	.min_core_ib = 2400000,

	.min_llcc_ib = 0, /* No LLCC on this SoC */

	.min_dram_ib = 800000,

	.min_prefill_lines = 24,

	.danger_lut_tbl = {0xf, 0xffff, 0x0},

	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},

	.qos_lut_tbl = {

		{.nentry = ARRAY_SIZE(sm8150_qos_linear),

		.entries = sm8150_qos_linear

		},

		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),

		.entries = sc7180_qos_macrotile

		},

		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),

		.entries = sc7180_qos_nrt

		},

		/* TODO: macrotile-qseed is different from macrotile */

	},

	.cdp_cfg = {

		{.rd_enable = 1, .wr_enable = 1},

		{.rd_enable = 1, .wr_enable = 0}

	},

	.clk_inefficiency_factor = 105,

	.bw_inefficiency_factor = 120,

};



static const struct dpu_mdss_version sm6125_mdss_ver = {

	.core_major_ver = 5,

	.core_minor_ver = 4,

};



const struct dpu_mdss_cfg dpu_sm6125_cfg = {

	.mdss_ver = &sm6125_mdss_ver,

	.caps = &sm6125_dpu_caps,

	.ubwc = &sm6125_ubwc_cfg,

	.mdp = &sm6125_mdp,

	.ctl_count = ARRAY_SIZE(sm6125_ctl),

	.ctl = sm6125_ctl,

	.sspp_count = ARRAY_SIZE(sm6125_sspp),

	.sspp = sm6125_sspp,

	.mixer_count = ARRAY_SIZE(sm6125_lm),

	.mixer = sm6125_lm,

	.dspp_count = ARRAY_SIZE(sm6125_dspp),

	.dspp = sm6125_dspp,

	.pingpong_count = ARRAY_SIZE(sm6125_pp),

	.pingpong = sm6125_pp,

	.intf_count = ARRAY_SIZE(sm6125_intf),

	.intf = sm6125_intf,

	.vbif_count = ARRAY_SIZE(sdm845_vbif),

	.vbif = sdm845_vbif,

	.perf = &sm6125_perf_data,

	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \

		     BIT(MDP_SSPP_TOP0_INTR2) | \

		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \

		     BIT(MDP_INTF0_INTR) | \

		     BIT(MDP_INTF1_INTR) | \

		     BIT(MDP_INTF1_TEAR_INTR),

};



#endif

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+7 −0
Original line number Diff line number Diff line
@@ -33,6 +33,9 @@ 
#define VIG_SC7180_MASK \

	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))



#define VIG_SM6125_MASK \

	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))



#define VIG_SC7180_MASK_SDMA \

	(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
@@ -333,6 +336,9 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = 
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =

				_VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4);



static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =

				_VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE);



static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =

				_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4);

static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
@@ -632,6 +638,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 


#include "catalog/dpu_5_0_sm8150.h"

#include "catalog/dpu_5_1_sc8180x.h"

#include "catalog/dpu_5_4_sm6125.h"



#include "catalog/dpu_6_0_sm8250.h"

#include "catalog/dpu_6_2_sc7180.h"

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+1 −0
Original line number Diff line number Diff line
@@ -871,6 +871,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; 
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;

extern const struct dpu_mdss_cfg dpu_sc7180_cfg;

extern const struct dpu_mdss_cfg dpu_sm6115_cfg;

extern const struct dpu_mdss_cfg dpu_sm6125_cfg;

extern const struct dpu_mdss_cfg dpu_sm6350_cfg;

extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;

extern const struct dpu_mdss_cfg dpu_sm6375_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

+1 −0
Original line number Diff line number Diff line
@@ -1346,6 +1346,7 @@ static const struct of_device_id dpu_dt_match[] = { 
	{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },

	{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },

	{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },

	{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },

	{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },

	{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },

	{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },