Commit 9b8ffea6 authored by Vincent Wan's avatar Vincent Wan Committed by Ulf Hansson
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mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data 



SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms

Signed-off-by: default avatarVincent Wan <vincent.wan@amd.com>
Signed-off-by: default avatarWan Zongshun <mcuos.com@gmail.com>
Signed-off-by: default avatarArindam Nath <arindam.nath@amd.com>
Tested-by: default avatarVikram B <vikram.b@amd.com>
Tested-by: default avatarRaghavendra Swamy <raghavendra.swamy@amd.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent ad89fcb2

drivers/mmc/host/sdhci.c

+7 −2
Original line number Diff line number Diff line
@@ -915,10 +915,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, 
	struct mmc_data *data = cmd->data;



	if (data == NULL) {

		if (host->quirks2 &

			SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {

			sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);

		} else {

		/* clear Auto CMD settings for no data CMDs */

			mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);

			sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |

				SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);

		}

		return;

	}

include/linux/mmc/sdhci.h

+2 −0
Original line number Diff line number Diff line
@@ -102,6 +102,8 @@ struct sdhci_host { 
#define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)

/* Controller does not support 64-bit DMA */

#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA			(1<<9)

/* need clear transfer mode register before send cmd */

#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)



	int irq;		/* Device IRQ */

	void __iomem *ioaddr;	/* Mapped address */