Loading drivers/gpio/gpio-pch.c +6 −8 Original line number Diff line number Diff line Loading @@ -313,17 +313,15 @@ static void pch_irq_ack(struct irq_data *d) static irqreturn_t pch_gpio_handler(int irq, void *dev_id) { struct pch_gpio *chip = dev_id; u32 reg_val = ioread32(&chip->reg->istatus); unsigned long reg_val = ioread32(&chip->reg->istatus); int i, ret = IRQ_NONE; for (i = 0; i < gpio_pins[chip->ioh]; i++) { if (reg_val & BIT(i)) { dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n", __func__, i, irq, reg_val); for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) { dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%lx\n", __func__, i, irq, reg_val); generic_handle_irq(chip->irq_base + i); ret = IRQ_HANDLED; } } return ret; } Loading Loading
drivers/gpio/gpio-pch.c +6 −8 Original line number Diff line number Diff line Loading @@ -313,17 +313,15 @@ static void pch_irq_ack(struct irq_data *d) static irqreturn_t pch_gpio_handler(int irq, void *dev_id) { struct pch_gpio *chip = dev_id; u32 reg_val = ioread32(&chip->reg->istatus); unsigned long reg_val = ioread32(&chip->reg->istatus); int i, ret = IRQ_NONE; for (i = 0; i < gpio_pins[chip->ioh]; i++) { if (reg_val & BIT(i)) { dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n", __func__, i, irq, reg_val); for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) { dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%lx\n", __func__, i, irq, reg_val); generic_handle_irq(chip->irq_base + i); ret = IRQ_HANDLED; } } return ret; } Loading