Merge tag 'clk-meson-dt-v5.6-1' of https://github.com/BayLibre/clk-meson into v5.6/dt

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic DDR Clock Controller Device Tree Bindings

maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

properties:

  compatible:

    enum:

      - amlogic,meson8-ddr-clkc

      - amlogic,meson8b-ddr-clkc

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  clock-names:

    items:

      - const: xtal

  "#clock-cells":

    const: 1

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"

additionalProperties: false

examples:

  - |

    ddr_clkc: clock-controller@400 {

      compatible = "amlogic,meson8-ddr-clkc";

      reg = <0x400 0x20>;

      clocks = <&xtal>;

      clock-names = "xtal";

      #clock-cells = <1>;

    };

...

	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

- #clock-cells: should be 1.

- #reset-cells: should be 1.

- clocks: list of clock phandles, one for each entry in clock-names

- clock-names: should contain the following:

  * "xtal": the 24MHz system oscillator

  * "ddr_pll": the DDR PLL clock

  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)

Parent node should have the following properties :

- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

/* SPDX-License-Identifier: GPL-2.0 */

#define DDR_CLKID_DDR_PLL_DCO			0

#define DDR_CLKID_DDR_PLL			1