Unverified Commit 9e43c9a8 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Mark Brown
Browse files

spi: pxa2xx: Utilize MMIO and physical base from struct ssp_device



We have a duplication of MMIO and physical base addresses in
the struct driver_data, get rid of it and reuse members from
struct ssp_device instead.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210423182441.50272-3-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f2eed8ca
Loading
Loading
Loading
Loading
+2 −2
Original line number Diff line number Diff line
@@ -94,14 +94,14 @@ pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
	cfg.direction = dir;

	if (dir == DMA_MEM_TO_DEV) {
		cfg.dst_addr = drv_data->ssdr_physical;
		cfg.dst_addr = drv_data->ssp->phys_base + SSDR;
		cfg.dst_addr_width = width;
		cfg.dst_maxburst = chip->dma_burst_size;

		sgt = &xfer->tx_sg;
		chan = drv_data->controller->dma_tx;
	} else {
		cfg.src_addr = drv_data->ssdr_physical;
		cfg.src_addr = drv_data->ssp->phys_base + SSDR;
		cfg.src_addr_width = width;
		cfg.src_maxburst = chip->dma_burst_size;

+1 −3
Original line number Diff line number Diff line
@@ -325,7 +325,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
	u32 value;

	config = lpss_get_config(drv_data);
	drv_data->lpss_base = drv_data->ioaddr + config->offset;
	drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;

	/* Enable software chip select control */
	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
@@ -1733,8 +1733,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)

	drv_data->ssp_type = ssp->type;

	drv_data->ioaddr = ssp->mmio_base;
	drv_data->ssdr_physical = ssp->phys_base + SSDR;
	if (pxa25x_ssp_comp(drv_data)) {
		switch (drv_data->ssp_type) {
		case QUARK_X1000_SSP:
+4 −10
Original line number Diff line number Diff line
@@ -33,10 +33,6 @@ struct driver_data {
	/* PXA hookup */
	struct pxa2xx_spi_controller *controller_info;

	/* SSP register addresses */
	void __iomem *ioaddr;
	phys_addr_t ssdr_physical;

	/* SSP masks*/
	u32 dma_cr1;
	u32 int_cr1;
@@ -87,16 +83,14 @@ struct chip_data {
	void (*cs_control)(u32 command);
};

static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
				  unsigned reg)
static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
{
	return __raw_readl(drv_data->ioaddr + reg);
	return pxa_ssp_read_reg(drv_data->ssp, reg);
}

static  inline void pxa2xx_spi_write(const struct driver_data *drv_data,
				     unsigned reg, u32 val)
static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
{
	__raw_writel(val, drv_data->ioaddr + reg);
	pxa_ssp_write_reg(drv_data->ssp, reg, val);
}

#define DMA_ALIGNMENT		8