Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 (9e4b0d55) · Commits · jan.koester / Linux

Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml

0 → 100644

+45 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Intel Keem Bay OCS AES Device Tree Bindings

		maintainers:
		- Daniele Alessandrelli <daniele.alessandrelli@intel.com>

		description:
		The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides
		hardware-accelerated AES/SM4 encryption/decryption.

		properties:
		compatible:
		const: intel,keembay-ocs-aes

		reg:
		maxItems: 1

		interrupts:
		maxItems: 1

		clocks:
		maxItems: 1

		required:
		- compatible
		- reg
		- interrupts
		- clocks

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		crypto@30008000 {
		compatible = "intel,keembay-ocs-aes";
		reg = <0x30008000 0x1000>;
		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scmi_clk 95>;
		};

+12 −2

Original line number	Diff line number	Diff line
		@@ -8016,7 +8016,7 @@ F: drivers/staging/hikey9xx/
		HISILICON TRUE RANDOM NUMBER GENERATOR V2 SUPPORT
		M: Zaibo Xu <xuzaibo@huawei.com>
		S: Maintained
		F: drivers/char/hw_random/hisi-trng-v2.c
		F: drivers/crypto/hisilicon/trng/trng.c

		HISILICON V3XX SPI NOR FLASH Controller Driver
		M: John Garry <john.garry@huawei.com>
		@@ -8982,6 +8982,16 @@ S: Maintained
		F: Documentation/devicetree/bindings/display/intel,kmb_display.yaml
		F: drivers/gpu/drm/kmb/

		INTEL KEEM BAY OCS AES/SM4 CRYPTO DRIVER
		M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
		S: Maintained
		F: Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml
		F: drivers/crypto/keembay/Kconfig
		F: drivers/crypto/keembay/Makefile
		F: drivers/crypto/keembay/keembay-ocs-aes-core.c
		F: drivers/crypto/keembay/ocs-aes.c
		F: drivers/crypto/keembay/ocs-aes.h

		INTEL MANAGEMENT ENGINE (mei)
		M: Tomas Winkler <tomas.winkler@intel.com>
		L: linux-kernel@vger.kernel.org

+22 −10

Original line number	Diff line number	Diff line
		@@ -386,20 +386,32 @@ ENTRY(ce_aes_ctr_encrypt)
		.Lctrloop4x:
		subs r4, r4, #4
		bmi .Lctr1x
		add r6, r6, #1

		/*
		* NOTE: the sequence below has been carefully tweaked to avoid
		* a silicon erratum that exists in Cortex-A57 (#1742098) and
		* Cortex-A72 (#1655431) cores, where AESE/AESMC instruction pairs
		* may produce an incorrect result if they take their input from a
		* register of which a single 32-bit lane has been updated the last
		* time it was modified. To work around this, the lanes of registers
		* q0-q3 below are not manipulated individually, and the different
		* counter values are prepared by successive manipulations of q7.
		*/
		add ip, r6, #1
		vmov q0, q7
		rev ip, ip
		add lr, r6, #2
		vmov s31, ip @ set lane 3 of q1 via q7
		add ip, r6, #3
		rev lr, lr
		vmov q1, q7
		rev ip, r6
		add r6, r6, #1
		vmov s31, lr @ set lane 3 of q2 via q7
		rev ip, ip
		vmov q2, q7
		vmov s7, ip
		rev ip, r6
		add r6, r6, #1
		vmov s31, ip @ set lane 3 of q3 via q7
		add r6, r6, #4
		vmov q3, q7
		vmov s11, ip
		rev ip, r6
		add r6, r6, #1
		vmov s15, ip

		vld1.8 {q4-q5}, [r1]!
		vld1.8 {q6}, [r1]!
		vld1.8 {q15}, [r1]!

+5 −3

Original line number	Diff line number	Diff line
		@@ -19,7 +19,7 @@ MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
		MODULE_LICENSE("GPL v2");

		MODULE_ALIAS_CRYPTO("ecb(aes)");
		MODULE_ALIAS_CRYPTO("cbc(aes)");
		MODULE_ALIAS_CRYPTO("cbc(aes)-all");
		MODULE_ALIAS_CRYPTO("ctr(aes)");
		MODULE_ALIAS_CRYPTO("xts(aes)");

		@@ -191,7 +191,8 @@ static int cbc_init(struct crypto_skcipher *tfm)
		struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
		unsigned int reqsize;

		ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
		ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC \|
		CRYPTO_ALG_NEED_FALLBACK);
		if (IS_ERR(ctx->enc_tfm))
		return PTR_ERR(ctx->enc_tfm);

		@@ -441,7 +442,8 @@ static struct skcipher_alg aes_algs[] = { {
		.base.cra_blocksize = AES_BLOCK_SIZE,
		.base.cra_ctxsize = sizeof(struct aesbs_cbc_ctx),
		.base.cra_module = THIS_MODULE,
		.base.cra_flags = CRYPTO_ALG_INTERNAL,
		.base.cra_flags = CRYPTO_ALG_INTERNAL \|
		CRYPTO_ALG_NEED_FALLBACK,

		.min_keysize = AES_MIN_KEY_SIZE,
		.max_keysize = AES_MAX_KEY_SIZE,

+17 −17

Original line number	Diff line number	Diff line
		@@ -23,7 +23,7 @@
		asmlinkage void chacha_block_xor_neon(const u32 state, u8 dst, const u8 *src,
		int nrounds);
		asmlinkage void chacha_4block_xor_neon(const u32 state, u8 dst, const u8 *src,
		int nrounds);
		int nrounds, unsigned int nbytes);
		asmlinkage void hchacha_block_arm(const u32 state, u32 out, int nrounds);
		asmlinkage void hchacha_block_neon(const u32 state, u32 out, int nrounds);

		@@ -42,23 +42,23 @@ static void chacha_doneon(u32 state, u8 dst, const u8 *src,
		{
		u8 buf[CHACHA_BLOCK_SIZE];

		while (bytes >= CHACHA_BLOCK_SIZE * 4) {
		chacha_4block_xor_neon(state, dst, src, nrounds);
		bytes -= CHACHA_BLOCK_SIZE * 4;
		src += CHACHA_BLOCK_SIZE * 4;
		dst += CHACHA_BLOCK_SIZE * 4;
		state[12] += 4;
		}
		while (bytes >= CHACHA_BLOCK_SIZE) {
		chacha_block_xor_neon(state, dst, src, nrounds);
		bytes -= CHACHA_BLOCK_SIZE;
		src += CHACHA_BLOCK_SIZE;
		dst += CHACHA_BLOCK_SIZE;
		state[12]++;
		while (bytes > CHACHA_BLOCK_SIZE) {
		unsigned int l = min(bytes, CHACHA_BLOCK_SIZE * 4U);

		chacha_4block_xor_neon(state, dst, src, nrounds, l);
		bytes -= l;
		src += l;
		dst += l;
		state[12] += DIV_ROUND_UP(l, CHACHA_BLOCK_SIZE);
		}
		if (bytes) {
		memcpy(buf, src, bytes);
		chacha_block_xor_neon(state, buf, buf, nrounds);
		const u8 *s = src;
		u8 *d = dst;

		if (bytes != CHACHA_BLOCK_SIZE)
		s = d = memcpy(buf, src, bytes);
		chacha_block_xor_neon(state, d, s, nrounds);
		if (d != dst)
		memcpy(dst, buf, bytes);
		}
		}