Commit 9e98f8c7 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge tag 'mlx5-fixes-2022-07-28' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux 

Saeed Mahameed says:

====================
mlx5 fixes 2022-07-28

This series provides bug fixes to mlx5 driver.

* tag 'mlx5-fixes-2022-07-28' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux:
  net/mlx5: Fix driver use of uninitialized timeout
  net/mlx5: DR, Fix SMFS steering info dump format
  net/mlx5: Adjust log_max_qp to be 18 at most
  net/mlx5e: Modify slow path rules to go to slow fdb
  net/mlx5e: Fix calculations related to max MPWQE size
  net/mlx5e: xsk: Account for XSK RQ UMRs when calculating ICOSQ size
  net/mlx5e: Fix the value of MLX5E_MAX_RQ_NUM_MTTS
  net/mlx5e: TC, Fix post_act to not match on in_port metadata
  net/mlx5e: Remove WARN_ON when trying to offload an unsupported TLS cipher/version
====================

Link: https://lore.kernel.org/r/20220728204640.139990-1-saeed@kernel.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents b65a1534 42b4f7f6

drivers/net/ethernet/mellanox/mlx5/core/en.h

+11 −10
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ struct page_pool; 
#define MLX5E_REQUIRED_WQE_MTTS		(MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))

#define MLX5E_REQUIRED_MTTS(wqes)	(wqes * MLX5E_REQUIRED_WQE_MTTS)

#define MLX5E_MAX_RQ_NUM_MTTS	\

	((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */

	(ALIGN_DOWN(U16_MAX, 4) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */

#define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))

#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW	\

		(ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
@@ -174,8 +174,8 @@ struct page_pool; 
	ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_ALIGNMENT)



#define MLX5E_MAX_KLM_PER_WQE(mdev) \

	MLX5E_KLM_ENTRIES_PER_WQE(mlx5e_get_sw_max_sq_mpw_wqebbs(mlx5e_get_max_sq_wqebbs(mdev)) \

				   << MLX5_MKEY_BSF_OCTO_SIZE)

	MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * \

		mlx5e_get_sw_max_sq_mpw_wqebbs(mlx5e_get_max_sq_wqebbs(mdev)))



#define MLX5E_MSG_LEVEL			NETIF_MSG_LINK
@@ -233,7 +233,7 @@ static inline u16 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 
		     MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);

}



static inline u16 mlx5e_get_sw_max_sq_mpw_wqebbs(u16 max_sq_wqebbs)

static inline u8 mlx5e_get_sw_max_sq_mpw_wqebbs(u8 max_sq_wqebbs)

{

/* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.

 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
@@ -242,11 +242,12 @@ static inline u16 mlx5e_get_sw_max_sq_mpw_wqebbs(u16 max_sq_wqebbs) 
 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be

 * cache-aligned.

 */

#if L1_CACHE_BYTES < 128

	return min_t(u16, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);

#else

	return min_t(u16, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 2);

	u8 wqebbs = min_t(u8, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);



#if L1_CACHE_BYTES >= 128

	wqebbs = ALIGN_DOWN(wqebbs, 2);

#endif

	return wqebbs;

}



struct mlx5e_tx_wqe {
@@ -455,7 +456,7 @@ struct mlx5e_txqsq { 
	struct netdev_queue       *txq;

	u32                        sqn;

	u16                        stop_room;

	u16                        max_sq_mpw_wqebbs;

	u8                         max_sq_mpw_wqebbs;

	u8                         min_inline_mode;

	struct device             *pdev;

	__be32                     mkey_be;
@@ -570,7 +571,7 @@ struct mlx5e_xdpsq { 
	struct device             *pdev;

	__be32                     mkey_be;

	u16                        stop_room;

	u16                        max_sq_mpw_wqebbs;

	u8                         max_sq_mpw_wqebbs;

	u8                         min_inline_mode;

	unsigned long              state;

	unsigned int               hw_mtu;

drivers/net/ethernet/mellanox/mlx5/core/en/params.c

+12 −0
Original line number Diff line number Diff line
@@ -790,8 +790,20 @@ static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, 
		return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;



	wqebbs = MLX5E_UMR_WQEBBS * BIT(mlx5e_get_rq_log_wq_sz(rqp->rqc));



	/* If XDP program is attached, XSK may be turned on at any time without

	 * restarting the channel. ICOSQ must be big enough to fit UMR WQEs of

	 * both regular RQ and XSK RQ.

	 * Although mlx5e_mpwqe_get_log_rq_size accepts mlx5e_xsk_param, it

	 * doesn't affect its return value, as long as params->xdp_prog != NULL,

	 * so we can just multiply by 2.

	 */

	if (params->xdp_prog)

		wqebbs *= 2;



	if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)

		wqebbs += mlx5e_shampo_icosq_sz(mdev, params, rqp);



	return max_t(u8, MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE, order_base_2(wqebbs));

}

drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c

+1 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ mlx5e_tc_post_act_add(struct mlx5e_post_act *post_act, struct mlx5_flow_attr *at 
	post_attr->inner_match_level = MLX5_MATCH_NONE;

	post_attr->outer_match_level = MLX5_MATCH_NONE;

	post_attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_DECAP;

	post_attr->flags |= MLX5_ATTR_FLAG_NO_IN_PORT;



	handle->ns_type = post_act->ns_type;

	/* Splits were handled before post action */

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ static int mlx5e_ktls_add(struct net_device *netdev, struct sock *sk, 
	struct mlx5_core_dev *mdev = priv->mdev;

	int err;



	if (WARN_ON(!mlx5e_ktls_type_check(mdev, crypto_info)))

	if (!mlx5e_ktls_type_check(mdev, crypto_info))

		return -EOPNOTSUPP;



	if (direction == TLS_OFFLOAD_CTX_DIR_TX)

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c

+17 −6
Original line number Diff line number Diff line
@@ -230,10 +230,8 @@ esw_setup_ft_dest(struct mlx5_flow_destination *dest, 
}



static void

esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,

			 struct mlx5_flow_act *flow_act,

			 struct mlx5_fs_chains *chains,

			 int i)

esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,

		      struct mlx5_fs_chains *chains, int i)

{

	if (mlx5_chains_ignore_flow_level_supported(chains))

		flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
@@ -241,6 +239,16 @@ esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, 
	dest[i].ft = mlx5_chains_get_tc_end_ft(chains);

}



static void

esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,

			 struct mlx5_eswitch *esw, int i)

{

	if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))

		flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;

	dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;

	dest[i].ft = esw->fdb_table.offloads.slow_fdb;

}



static int

esw_setup_chain_dest(struct mlx5_flow_destination *dest,

		     struct mlx5_flow_act *flow_act,
@@ -475,8 +483,11 @@ esw_setup_dests(struct mlx5_flow_destination *dest, 
	} else if (attr->dest_ft) {

		esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);

		(*i)++;

	} else if (mlx5e_tc_attr_flags_skip(attr->flags)) {

		esw_setup_slow_path_dest(dest, flow_act, chains, *i);

	} else if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {

		esw_setup_slow_path_dest(dest, flow_act, esw, *i);

		(*i)++;

	} else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {

		esw_setup_accept_dest(dest, flow_act, chains, *i);

		(*i)++;

	} else if (attr->dest_chain) {

		err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,