Commit 9eb18ed7 authored by Johan Hovold's avatar Johan Hovold Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc8280xp: drop reference-clock source 



The source clock for the reference clock should not be described by the
devicetree binding and instead this relationship should be modelled in
the clock driver.

Update the USB PHY nodes to match the fixed binding.

Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111093857.11360-4-johan+linaro@kernel.org
parent 64ebe7fc

arch/arm64/boot/dts/qcom/sc8280xp.dtsi

+2 −6
Original line number Diff line number Diff line
@@ -1587,12 +1587,10 @@ usb_2_qmpphy0: phy@88ef000 { 
			reg = <0 0x088ef000 0 0x2000>;



			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_USB3_MP0_CLKREF_CLK>,

				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,

				 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;

			clock-names = "aux", "ref_clk_src", "ref", "com_aux",

				      "pipe";

			clock-names = "aux", "ref", "com_aux", "pipe";



			resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,

				 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
@@ -1613,12 +1611,10 @@ usb_2_qmpphy1: phy@88f1000 { 
			reg = <0 0x088f1000 0 0x2000>;



			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_USB3_MP1_CLKREF_CLK>,

				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,

				 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;

			clock-names = "aux", "ref_clk_src", "ref", "com_aux",

				      "pipe";

			clock-names = "aux", "ref", "com_aux", "pipe";



			resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,

				 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;