Commit 9ee20ee6 authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Implement tmz surface. 



Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0d18d7bb

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ enum dc_plane_addr_type { 


struct dc_plane_address {

	enum dc_plane_addr_type type;

	bool tmz_surface;

	union {

		struct{

			PHYSICAL_ADDRESS_LOC addr;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c

+10 −0
Original line number Diff line number Diff line
@@ -266,6 +266,9 @@ static bool min10_program_surface_flip_and_addr( 
		if (address->grph.addr.quad_part == 0)

			break;



		REG_UPDATE(DCSURF_SURFACE_CONTROL,

				PRIMARY_SURFACE_TMZ, address->tmz_surface);



		if (address->grph.meta_addr.quad_part != 0) {

			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

					PRIMARY_META_SURFACE_ADDRESS_HIGH,
@@ -289,6 +292,9 @@ static bool min10_program_surface_flip_and_addr( 
			|| address->video_progressive.chroma_addr.quad_part == 0)

			break;



		REG_UPDATE(DCSURF_SURFACE_CONTROL,

				PRIMARY_SURFACE_TMZ, address->tmz_surface);



		if (address->video_progressive.luma_meta_addr.quad_part != 0) {

			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

				PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
@@ -328,6 +334,10 @@ static bool min10_program_surface_flip_and_addr( 
			break;

		if (address->grph_stereo.right_addr.quad_part == 0)

			break;



		REG_UPDATE(DCSURF_SURFACE_CONTROL,

				PRIMARY_SURFACE_TMZ, address->tmz_surface);



		if (address->grph_stereo.right_meta_addr.quad_part != 0) {



			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h

+2 −0
Original line number Diff line number Diff line
@@ -303,6 +303,7 @@ struct dcn_mi_registers { 
	MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\

	MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\

	MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\

	MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\

	MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\

	MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\

	MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
@@ -453,6 +454,7 @@ struct dcn_mi_registers { 
	type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\

	type SURFACE_EARLIEST_INUSE_ADDRESS_C;\

	type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\

	type PRIMARY_SURFACE_TMZ;\

	type PRIMARY_SURFACE_DCC_EN;\

	type PRIMARY_SURFACE_DCC_IND_64B_BLK;\

	type DET_BUF_PLANE1_BASE_ADDRESS;\