Commit 9f0d16eb authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm-dt-for-v5.9-tag1' of... 

Merge tag 'renesas-arm-dt-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.9

  - Increase support for the Renesas RZ/G1H SoC on the iWave RainboW
    Qseven board (G21D), and its camera expansion board,
  - IPMMU support for R-Car M3-W+,
  - Support for Rev.3.0/4.0 of the HopeRun HiHope RZ/G2M and RZ/G2N
    boards,
  - Minor fixes and improvements.

* tag 'renesas-arm-dt-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (36 commits)
  ARM: dts: r8a7778: Enable IRLM setup via DT
  arm64: dts: renesas: Add HiHope RZ/G2N Rev2.0/3.0/4.0 board with idk-1110wr display
  arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 sub board support
  arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 main board support
  arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 board with idk-1110wr display
  arm64: dts: renesas: hihope-rzg2-ex: Separate out lvds specific nodes into common file
  arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 sub board support
  arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 main board support
  arm64: dts: renesas: Add HiHope RZ/G2M[N] Rev.3.0/4.0 specific into common file
  arm64: dts: renesas: hihope-common: Separate out Rev.2.0 specific into hihope-rev2.dtsi file
  arm64: dts: renesas: r8a774b1-hihope-rzg2n[-ex]: Rename HiHope RZ/G2N boards
  arm64: dts: renesas: r8a774a1-hihope-rzg2m[-ex/-ex-idk-1110wr]: Rename HiHope RZ/G2M boards
  arm64: dts: renesas: r8a77961: Add IPMMU nodes
  ARM: dts: r8a7742: Add MSIOF[0123] support
  ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add device tree for camera DB
  ARM: dts: r8a7742: Add CMT SoC specific support
  ARM: dts: r8a7742: Add thermal device to DT
  ARM: dts: r8a7742-iwg21d-q7: Sound DMA support via DVC on DTS
  ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec
  ARM: dts: r8a7742: Add audio support
  ...

Link: https://lore.kernel.org/r/20200703120642.5128-3-geert+renesas@glider.be


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 48778464 b7f13b91

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -927,6 +927,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ 
	r8a73a4-ape6evm.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7742-iwg21d-q7.dtb \

	r8a7742-iwg21d-q7-dbcm-ca.dtb \

	r8a7743-iwg20d-q7.dtb \

	r8a7743-iwg20d-q7-dbcm-ca.dtb \

	r8a7743-sk-rzg1m.dtb \

arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts

0 → 100644
+97 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for the iWave-RZ/G1H Qseven board development

 * platform with camera daughter board

 *

 * Copyright (C) 2020 Renesas Electronics Corp.

 */



/dts-v1/;

#include "r8a7742-iwg21d-q7.dts"



/ {

	model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";

	compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";



	aliases {

		serial0 = &scif0;

		serial1 = &scif1;

		serial3 = &scifb1;

		serial5 = &hscif0;

		ethernet1 = &ether;

	};

};



&avb {

	/* Pins shared with VIN0, keep status disabled */

	status = "disabled";

};



&ether {

	pinctrl-0 = <&ether_pins>;

	pinctrl-names = "default";



	phy-handle = <&phy1>;

	renesas,ether-link-active-low;

	status = "okay";



	phy1: ethernet-phy@1 {

		reg = <1>;

		micrel,led-mode = <1>;

	};

};



&hscif0 {

	pinctrl-0 = <&hscif0_pins>;

	pinctrl-names = "default";

	uart-has-rtscts;

	status = "okay";

};



&pfc {

	ether_pins: ether {

		groups = "eth_mdio", "eth_rmii";

		function = "eth";

	};



	hscif0_pins: hscif0 {

		groups = "hscif0_data", "hscif0_ctrl";

		function = "hscif0";

	};



	scif0_pins: scif0 {

		groups = "scif0_data";

		function = "scif0";

	};



	scif1_pins: scif1 {

		groups = "scif1_data";

		function = "scif1";

	};



	scifb1_pins: scifb1 {

		groups = "scifb1_data";

		function = "scifb1";

	};

};



&scif0 {

	pinctrl-0 = <&scif0_pins>;

	pinctrl-names = "default";

	status = "okay";

};



&scif1 {

	pinctrl-0 = <&scif1_pins>;

	pinctrl-names = "default";

	status = "okay";

};



&scifb1 {

	pinctrl-0 = <&scifb1_pins>;

	pinctrl-names = "default";

	status = "okay";



	rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;

	cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;

};

arch/arm/boot/dts/r8a7742-iwg21d-q7.dts

+187 −0
Original line number Diff line number Diff line
@@ -5,6 +5,29 @@ 
 * Copyright (C) 2020 Renesas Electronics Corp.

 */



/*

 * SSI-SGTL5000

 *

 * This command is required when Playback/Capture

 *

 *      amixer set "DVC Out" 100%

 *      amixer set "DVC In" 100%

 *

 * You can use Mute

 *

 *      amixer set "DVC Out Mute" on

 *      amixer set "DVC In Mute" on

 *

 * You can use Volume Ramp

 *

 *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"

 *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"

 *      amixer set "DVC Out Ramp" on

 *      aplay xxx.wav &

 *      amixer set "DVC Out"  80%  // Volume Down

 *      amixer set "DVC Out" 100%  // Volume Up

 */



/dts-v1/;

#include "r8a7742-iwg21m.dtsi"
@@ -14,19 +37,158 @@ / { 


	aliases {

		serial2 = &scifa2;

		serial4 = &scifb2;

		ethernet0 = &avb;

	};



	chosen {

		bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait";

		stdout-path = "serial2:115200n8";

	};



	audio_clock: audio_clock {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <26000000>;

	};



	reg_1p5v: 1p5v {

		compatible = "regulator-fixed";

		regulator-name = "1P5V";

		regulator-min-microvolt = <1500000>;

		regulator-max-microvolt = <1500000>;

		regulator-always-on;

	};



	rsnd_sgtl5000: sound {

		compatible = "simple-audio-card";

		simple-audio-card,format = "i2s";

		simple-audio-card,bitclock-master = <&sndcodec>;

		simple-audio-card,frame-master = <&sndcodec>;



		sndcpu: simple-audio-card,cpu {

			sound-dai = <&rcar_sound>;

		};



		sndcodec: simple-audio-card,codec {

			sound-dai = <&sgtl5000>;

		};

	};



	vcc_sdhi2: regulator-vcc-sdhi2 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI2 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;

	};



	vccq_sdhi2: regulator-vccq-sdhi2 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI2 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1>, <1800000 0>;

	};

};



&avb {

	pinctrl-0 = <&avb_pins>;

	pinctrl-names = "default";



	phy-handle = <&phy3>;

	phy-mode = "gmii";

	renesas,no-ether-link;

	status = "okay";



	phy3: ethernet-phy@3 {

		reg = <3>;

		micrel,led-mode = <1>;

	};

};



&i2c2 {

	pinctrl-0 = <&i2c2_pins>;

	pinctrl-names = "default";



	status = "okay";

	clock-frequency = <400000>;



	sgtl5000: codec@a {

		compatible = "fsl,sgtl5000";

		#sound-dai-cells = <0>;

		reg = <0x0a>;

		clocks = <&audio_clock>;

		VDDA-supply = <&reg_3p3v>;

		VDDIO-supply = <&reg_3p3v>;

		VDDD-supply = <&reg_1p5v>;

	};

};



&pfc {

	avb_pins: avb {

		groups = "avb_mdio", "avb_gmii";

		function = "avb";

	};



	i2c2_pins: i2c2 {

		groups = "i2c2_b";

		function = "i2c2";

	};



	scifa2_pins: scifa2 {

		groups = "scifa2_data_c";

		function = "scifa2";

	};



	scifb2_pins: scifb2 {

		groups = "scifb2_data", "scifb2_ctrl";

		function = "scifb2";

	};



	sdhi2_pins: sd2 {

		groups = "sdhi2_data4", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <3300>;

	};



	sdhi2_pins_uhs: sd2_uhs {

		groups = "sdhi2_data4", "sdhi2_ctrl";

		function = "sdhi2";

		power-source = <1800>;

	};



	sound_pins: sound {

		groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";

		function = "ssi";

	};

};



&rcar_sound {

	pinctrl-0 = <&sound_pins>;

	pinctrl-names = "default";

	status = "okay";



	/* Single DAI */

	#sound-dai-cells = <0>;



	rcar_sound,dai {

		dai0 {

			playback = <&ssi4 &src4 &dvc1>;

			capture = <&ssi3 &src3 &dvc0>;

		};

	};

};



&rwdt {

	timeout-sec = <60>;

	status = "okay";

};



&scifa2 {
@@ -35,3 +197,28 @@ &scifa2 { 


	status = "okay";

};



&scifb2 {

	pinctrl-0 = <&scifb2_pins>;

	pinctrl-names = "default";



	uart-has-rtscts;

	status = "okay";

};



&sdhi2 {

	pinctrl-0 = <&sdhi2_pins>;

	pinctrl-1 = <&sdhi2_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi2>;

	vqmmc-supply = <&vccq_sdhi2>;

	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;

	sd-uhs-sdr50;

	status = "okay";

};



&ssi4 {

	shared-pin;

};

arch/arm/boot/dts/r8a7742.dtsi

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File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/r8a7778.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -78,7 +78,8 @@ irqpin: interrupt-controller@fe78001c { 
			<0xfe780010 4>,

			<0xfe780024 4>,

			<0xfe780044 4>,

			<0xfe780064 4>;

			<0xfe780064 4>,

			<0xfe780000 4>;

		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,