Commit 9faa4237 authored by Andrey Grodzovsky's avatar Andrey Grodzovsky Committed by Alex Deucher
Browse files

drm/amd/display: Fix s3 hang on resume. 



Avoid enabling CRTC_VERTICAL_INTERRUPT0 twice on resume.
It's enabled once from within manage_dm_interrupts in mode set
and another explicitly from amdgpu_dm_irq_resume_late.
Seems it lead to CRTC hang.

Signed-off-by: default avatarAndrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: default avatarAndrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7160c74c

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −1
Original line number Diff line number Diff line
@@ -575,7 +575,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) 


	ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);



	amdgpu_dm_irq_resume(adev);

	amdgpu_dm_irq_resume_late(adev);



	return ret;

}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

+11 −5
Original line number Diff line number Diff line
@@ -504,8 +504,11 @@ int amdgpu_dm_irq_suspend( 


	DRM_DEBUG_KMS("DM_IRQ: suspend\n");



	/* disable HW interrupt */

	for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) {

	/**

	 * Disable HW interrupt  for HPD and HPDRX only since FLIP and VBLANK

	 * will be disabled from manage_dm_interrupts on disable CRTC.

	 */

	for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6RX; src++) {

		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;

		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];

		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
@@ -544,7 +547,7 @@ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev) 
	return 0;

}



int amdgpu_dm_irq_resume(struct amdgpu_device *adev)

int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)

{

	int src;

	struct list_head *hnd_list_h, *hnd_list_l;
@@ -554,8 +557,11 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev) 


	DRM_DEBUG_KMS("DM_IRQ: resume\n");



	/* re-enable HW interrupt */

	for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) {

	/**

	 * Renable HW interrupt  for HPD and only since FLIP and VBLANK

	 * will be enabled from manage_dm_interrupts on enable CRTC.

	 */

	for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6; src++) {

		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;

		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];

		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h

+1 −1
Original line number Diff line number Diff line
@@ -117,6 +117,6 @@ int amdgpu_dm_irq_suspend(struct amdgpu_device *adev); 
 *

 */

int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);

int amdgpu_dm_irq_resume(struct amdgpu_device *adev);

int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);



#endif /* __AMDGPU_DM_IRQ_H__ */