Commit 9ff3dba6 authored by Xiaojie Yuan's avatar Xiaojie Yuan Committed by Alex Deucher
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drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12



Same as other navi asics.

Signed-off-by: default avatarXiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 716e9bb0
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+1 −0
Original line number Diff line number Diff line
@@ -1228,6 +1228,7 @@ static int gfx_v10_0_sw_init(void *handle)
	switch (adev->asic_type) {
	case CHIP_NAVI10:
	case CHIP_NAVI14:
	case CHIP_NAVI12:
		adev->gfx.me.num_me = 1;
		adev->gfx.me.num_pipe_per_me = 2;
		adev->gfx.me.num_queue_per_pipe = 1;