Commit a0660529 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'amlogic-dt' of... 

Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

ARM: dts: amlogic updates for v5.9
- power-domain and MMC updates

* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM: dts: meson8b: odroidc1: enable the SDHC controller
  ARM: dts: meson8b: ec100: enable the SDHC controller
  ARM: dts: meson: add the SDHC MMC controller
  ARM: dts: meson8b: add power domain controller
  ARM: dts: meson8m2: add resets for the power domain controller
  ARM: dts: meson8: add power domain controller

Link: https://lore.kernel.org/r/7hd04uf2o8.fsf@baylibre.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 6760a29c d6a3873c

arch/arm/boot/dts/meson.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -140,6 +140,13 @@ spifc: spi@8c80 { 
				status = "disabled";

			};



			sdhc: mmc@8e00 {

				compatible = "amlogic,meson-mx-sdhc";

				reg = <0x8e00 0x42>;

				interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;

				status = "disabled";

			};



			gpio_intc: interrupt-controller@9880 {

				compatible = "amlogic,meson-gpio-intc";

				reg = <0x9880 0x10>;

arch/arm/boot/dts/meson8.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <dt-bindings/clock/meson8-ddr-clkc.h>

#include <dt-bindings/clock/meson8b-clkc.h>

#include <dt-bindings/gpio/meson8-gpio.h>

#include <dt-bindings/power/meson8-power.h>

#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>

#include <dt-bindings/reset/amlogic,meson8b-reset.h>

#include "meson.dtsi"
@@ -385,6 +386,15 @@ mux { 
			};

		};



		sdxc_b_pins: sdxc-b {

			mux {

				groups = "sdxc_d0_b", "sdxc_d13_b",

					 "sdxc_clk_b", "sdxc_cmd_b";

				function = "sdxc_b";

				bias-pull-up;

			};

		};



		spi_nor_pins: nor {

			mux {

				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
@@ -454,6 +464,8 @@ temperature_calib: calib@1f4 { 
&ethmac {

	clocks = <&clkc CLKID_ETH>;

	clock-names = "stmmaceth";



	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;

};



&gpio_intc {
@@ -469,6 +481,16 @@ clkc: clock-controller { 
		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	pwrc: power-controller {

		compatible = "amlogic,meson8-pwrc";

		#power-domain-cells = <1>;

		amlogic,ao-sysctrl = <&pmu>;

		clocks = <&clkc CLKID_VPU>;

		clock-names = "vpu";

		assigned-clocks = <&clkc CLKID_VPU>;

		assigned-clock-rates = <364285714>;

	};

};



&hwrng {
@@ -547,6 +569,16 @@ &saradc { 
	nvmem-cell-names = "temperature_calib";

};



&sdhc {

	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";

	clocks = <&xtal>,

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_FCLK_DIV3>,

		 <&clkc CLKID_FCLK_DIV5>,

		 <&clkc CLKID_SDHC>;

	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";

};



&sdio {

	compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";

	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;

arch/arm/boot/dts/meson8b-ec100.dts

+25 −0
Original line number Diff line number Diff line
@@ -27,6 +27,11 @@ memory { 
		reg = <0x40000000 0x40000000>;

	};



	emmc_pwrseq: emmc-pwrseq {

		compatible = "mmc-pwrseq-emmc";

		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;

	};



	gpio-keys {

		compatible = "gpio-keys-polled";

		#address-cells = <1>;
@@ -299,6 +304,26 @@ &saradc { 
	vref-supply = <&vcc_1v8>;

};



&sdhc {

	status = "okay";



	pinctrl-0 = <&sdxc_c_pins>;

	pinctrl-names = "default";



	bus-width = <8>;

	max-frequency = <50000000>;



	cap-mmc-highspeed;

	disable-wp;

	non-removable;

	no-sdio;



	mmc-pwrseq = <&emmc_pwrseq>;



	vmmc-supply = <&vcc_3v3>;

	vqmmc-supply = <&vcc_3v3>;

};



&sdio {

	status = "okay";

arch/arm/boot/dts/meson8b-odroidc1.dts

+26 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ / { 
	aliases {

		serial0 = &uart_AO;

		mmc0 = &sd_card_slot;

		mmc1 = &sdhc;

	};



	chosen {
@@ -26,6 +27,11 @@ memory { 
		reg = <0x40000000 0x40000000>;

	};



	emmc_pwrseq: emmc-pwrseq {

		compatible = "mmc-pwrseq-emmc";

		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;

	};



	leds {

		compatible = "gpio-leds";

		blue {
@@ -310,6 +316,26 @@ &saradc { 
	vref-supply = <&vcc_1v8>;

};



&sdhc {

	status = "okay";



	pinctrl-0 = <&sdxc_c_pins>;

	pinctrl-names = "default";



	bus-width = <8>;

	max-frequency = <100000000>;



	disable-wp;

	cap-mmc-highspeed;

	mmc-hs200-1_8v;

	no-sdio;



	mmc-pwrseq = <&emmc_pwrseq>;



	vmmc-supply = <&vcc_3v3>;

	vqmmc-supply = <&vcc_1v8>;

};



&sdio {

	status = "okay";

arch/arm/boot/dts/meson8b.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <dt-bindings/clock/meson8-ddr-clkc.h>

#include <dt-bindings/clock/meson8b-clkc.h>

#include <dt-bindings/gpio/meson8b-gpio.h>

#include <dt-bindings/power/meson8-power.h>

#include <dt-bindings/reset/amlogic,meson8b-reset.h>

#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>

#include "meson.dtsi"
@@ -362,6 +363,16 @@ mux { 
			};

		};



		sdxc_c_pins: sdxc-c {

			mux {

				groups = "sdxc_d0_c", "sdxc_d13_c",

					 "sdxc_d47_c", "sdxc_clk_c",

					 "sdxc_cmd_c";

				function = "sdxc_c";

				bias-pull-up;

			};

		};



		pwm_c1_pins: pwm-c1 {

			mux {

				groups = "pwm_c1";
@@ -433,6 +444,8 @@ &ethmac { 


	resets = <&reset RESET_ETHERNET>;

	reset-names = "stmmaceth";



	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;

};



&gpio_intc {
@@ -449,6 +462,30 @@ clkc: clock-controller { 
		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	pwrc: power-controller {

		compatible = "amlogic,meson8b-pwrc";

		#power-domain-cells = <1>;

		amlogic,ao-sysctrl = <&pmu>;

		resets = <&reset RESET_DBLK>,

			 <&reset RESET_PIC_DC>,

			 <&reset RESET_HDMI_APB>,

			 <&reset RESET_HDMI_SYSTEM_RESET>,

			 <&reset RESET_VENCI>,

			 <&reset RESET_VENCP>,

			 <&reset RESET_VDAC_4>,

			 <&reset RESET_VENCL>,

			 <&reset RESET_VIU>,

			 <&reset RESET_VENC>,

			 <&reset RESET_RDMA>;

		reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",

			      "venci", "vencp", "vdac", "vencl", "viu",

			      "venc", "rdma";

		clocks = <&clkc CLKID_VPU>;

		clock-names = "vpu";

		assigned-clocks = <&clkc CLKID_VPU>;

		assigned-clock-rates = <182142857>;

	};

};



&hwrng {
@@ -527,6 +564,16 @@ &saradc { 
	nvmem-cell-names = "temperature_calib";

};



&sdhc {

	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";

	clocks = <&xtal>,

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_FCLK_DIV3>,

		 <&clkc CLKID_FCLK_DIV5>,

		 <&clkc CLKID_SDHC>;

	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";

};



&sdio {

	compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";

	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;