Commit a06ed27f authored by Nishanth Menon's avatar Nishanth Menon
Browse files

arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs 

Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.

Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.

[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438



Cc: stable@vger.kernel.org # 5.10+
Fixes: 2d87061e ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220215201008.15235-3-nm@ti.com
parent 8cae268b

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -76,7 +76,10 @@ gic500: interrupt-controller@1800000 { 
		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */

		      <0x00 0x01900000 0x00 0x100000>;	/* GICR */

		      <0x00 0x01900000 0x00 0x100000>,	/* GICR */

		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */

		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */

		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */



		/* vcpumntirq: virtual CPU interface maintenance interrupt */

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/ti/k3-j721e.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ cbass_main: bus@100000 { 
			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/

			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */

			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */

			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */

			 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */

			 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */

			 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */