Commit a19c1d00 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Unconfuse pre-icl vs. icl+ intel_sagv_{pre,post}_plane_update() 



intel_sagv_{pre,post}_plane_update() can accidentally forget
to bail out early on pre-icl and proceed down the icl+ codepath
at the end of the function. Fortunately it'll bail out before
it gets too far due to old_qgv_mask==new_qgv_mask==0 so no real
bug here. But lets make the code less confusing anyway.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220214091811.13725-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
parent c0299cc9

drivers/gpu/drm/i915/intel_pm.c

+6 −4
Original line number Diff line number Diff line
@@ -3802,7 +3802,8 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) 
	if (!new_bw_state)

		return;



	if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {

	if (DISPLAY_VER(dev_priv) < 11) {

		if (!intel_can_enable_sagv(dev_priv, new_bw_state))

			intel_disable_sagv(dev_priv);

		return;

	}
@@ -3853,7 +3854,8 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) 
	if (!new_bw_state)

		return;



	if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {

	if (DISPLAY_VER(dev_priv) < 11) {

		if (intel_can_enable_sagv(dev_priv, new_bw_state))

			intel_enable_sagv(dev_priv);

		return;

	}