ASoC: SOF: Intel: hda-mlink: HDaudio multi-link (a1d68507) · Commits · jan.koester / Linux

Documentation/sound/hd-audio/index.rst

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		@@ -9,3 +9,4 @@ HD-Audio
		controls
		dp-mst
		realtek-pc-beep
		intel-multi-link

Documentation/sound/hd-audio/intel-multi-link.rst

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		.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
		.. include:: <isonum.txt>

		================================================
		HDAudio multi-link extensions on Intel platforms
		================================================

		:Copyright: \|copy\| 2023 Intel Corporation

		This file documents the 'multi-link structure' introduced in 2015 with
		the Skylake processor and recently extended in newer Intel platforms

		HDaudio existing link mapping (2015 addition in SkyLake)
		========================================================

		External HDAudio codecs are handled with link #0, while iDISP codec
		for HDMI/DisplayPort is handled with link #1.

		The only change to the 2015 definitions is the declaration of the
		LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
		backwards-compatible change.

		LCTL.SPA and LCTL.CPA are automatically set when exiting reset. They
		are only used in existing drivers when the SCF value needs to be
		corrected.

		Basic structure for HDaudio codecs
		----------------------------------

		::

		+-----------+
		\| ML cap #0 \|
		+-----------+
		\| ML cap #1 \|---+
		+-----------+ \|
		\|
		+--> 0x0 +---------------+ LCAP
		\| ALT=0 \|
		+---------------+
		\| S192 \|
		+---------------+
		\| S96 \|
		+---------------+
		\| S48 \|
		+---------------+
		\| S24 \|
		+---------------+
		\| S12 \|
		+---------------+
		\| S6 \|
		+---------------+

		0x4 +---------------+ LCTL
		\| INTSTS \|
		+---------------+
		\| CPA \|
		+---------------+
		\| SPA \|
		+---------------+
		\| SCF \|
		+---------------+

		0x8 +---------------+ LOSIDV
		\| L1OSIVD15 \|
		+---------------+
		\| L1OSIDV.. \|
		+---------------+
		\| L1OSIDV1 \|
		+---------------+

		0xC +---------------+ LSDIID
		\| SDIID14 \|
		+---------------+
		\| SDIID... \|
		+---------------+
		\| SDIID0 \|
		+---------------+

		SoundWire HDaudio extended link mapping
		=======================================

		A SoundWire extended link is identified when LCAP.ALT=1 and
		LEPTR.ID=0.

		DMA control uses the existing LOSIDV register.

		Changes include additional descriptions for enumeration that were not
		present in earlier generations.

		- multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
		- number of sublinks (manager IP) in LCAP.LSCOUNT
		- power management moved from SHIM to LCTL.SPA bits
		- hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
		- mapping of SoundWire codecs to SDI ID bits
		- move of SHIM and Cadence registers to different offsets, with no
		change in functionality. The LEPTR.PTR value is an offset from the
		ML address, with a default value of 0x30000.

		Extended structure for SoundWire (assuming 4 Manager IP)
		--------------------------------------------------------

		::

		+-----------+
		\| ML cap #0 \|
		+-----------+
		\| ML cap #1 \|
		+-----------+
		\| ML cap #2 \|---+
		+-----------+ \|
		\|
		+--> 0x0 +---------------+ LCAP
		\| ALT=1 \|
		+---------------+
		\| INTC \|
		+---------------+
		\| OFLS \|
		+---------------+
		\| LSS \|
		+---------------+
		\| SLCOUNT=4 \|-----------+
		+---------------+ \|
		\|
		0x4 +---------------+ LCTL \|
		\| INTSTS \| \|
		+---------------+ \|
		\| CPA (x bits) \| \|
		+---------------+ \|
		\| SPA (x bits) \| \|
		+---------------+ for each sublink x
		\| INTEN \| \|
		+---------------+ \|
		\| OFLEN \| \|
		+---------------+ \|
		\|
		0x8 +---------------+ LOSIDV \|
		\| L1OSIVD15 \| \|
		+---------------+ \|
		\| L1OSIDV.. \| \|
		+---------------+ \|
		\| L1OSIDV1 \| +---+----------------------------------------------------------+
		+---------------+ \| \|
		v \|
		0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 \|
		\| SDIID14 \| \| \| SoundWire SHIM \| \|
		+---------------+ \| \| generic \| \|
		\| SDIID... \| \| +-----------------+ 0x00030100 \|
		+---------------+ \| \| SoundWire IP \| \|
		\| SDIID0 \| \| +-----------------+ 0x00036000 \|
		+---------------+ \| \| SoundWire SHIM \| \|
		\| \| vendor-specific \| \|
		0x1C +---------------+ LSYNC \| +-----------------+ \|
		\| CMDSYNC \| \| v
		+---------------+ \| +-----------------+ 0x00030000 + 0x8000 * x
		\| SYNCGO \| \| \| SoundWire SHIM \|
		+---------------+ \| \| generic \|
		\| SYNCPU \| \| +-----------------+ 0x00030100 + 0x8000 * x
		+---------------+ \| \| SoundWire IP \|
		\| SYNPRD \| \| +-----------------+ 0x00036000 + 0x8000 * x
		+---------------+ \| \| SoundWire SHIM \|
		\| \| vendor-specific \|
		0x20 +---------------+ LEPTR \| +-----------------+
		\| ID = 0 \| \|
		+---------------+ \|
		\| VER \| \|
		+---------------+ \|
		\| PTR \|------------+
		+---------------+


		DMIC HDaudio extended link mapping
		==================================

		A DMIC extended link is identified when LCAP.ALT=1 and
		LEPTR.ID=0xC1 are set.

		DMA control uses the existing LOSIDV register

		Changes include additional descriptions for enumeration that were not
		present in earlier generations.

		- multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
		- power management with LCTL.SPA bits
		- hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN

		- move of DMIC registers to different offsets, with no change in
		functionality. The LEPTR.PTR value is an offset from the ML
		address, with a default value of 0x10000.

		Extended structure for DMIC
		---------------------------

		::

		+-----------+
		\| ML cap #0 \|
		+-----------+
		\| ML cap #1 \|
		+-----------+
		\| ML cap #2 \|---+
		+-----------+ \|
		\|
		+--> 0x0 +---------------+ LCAP
		\| ALT=1 \|
		+---------------+
		\| INTC \|
		+---------------+
		\| OFLS \|
		+---------------+
		\| SLCOUNT=1 \|
		+---------------+

		0x4 +---------------+ LCTL
		\| INTSTS \|
		+---------------+
		\| CPA \|
		+---------------+
		\| SPA \|
		+---------------+
		\| INTEN \|
		+---------------+
		\| OFLEN \|
		+---------------+ +---> 0x10000 +-----------------+ 0x00010000
		\| \| DMIC SHIM \|
		0x8 +---------------+ LOSIDV \| \| generic \|
		\| L1OSIVD15 \| \| +-----------------+ 0x00010100
		+---------------+ \| \| DMIC IP \|
		\| L1OSIDV.. \| \| +-----------------+ 0x00016000
		+---------------+ \| \| DMIC SHIM \|
		\| L1OSIDV1 \| \| \| vendor-specific \|
		+---------------+ \| +-----------------+
		\|
		0x20 +---------------+ LEPTR \|
		\| ID = 0xC1 \| \|
		+---------------+ \|
		\| VER \| \|
		+---------------+ \|
		\| PTR \|-----------+
		+---------------+


		SSP HDaudio extended link mapping
		=================================

		A DMIC extended link is identified when LCAP.ALT=1 and
		LEPTR.ID=0xC0 are set.

		DMA control uses the existing LOSIDV register

		Changes include additional descriptions for enumeration and control that were not
		present in earlier generations:
		- number of sublinks (SSP IP instances) in LCAP.LSCOUNT
		- power management moved from SHIM to LCTL.SPA bits
		- hand-over to the DSP for access to multi-link registers, SHIM/IP
		with LCTL.OFLEN
		- move of SHIM and SSP IP registers to different offsets, with no
		change in functionality. The LEPTR.PTR value is an offset from the ML
		address, with a default value of 0x28000.

		Extended structure for SSP (assuming 3 instances of the IP)
		-----------------------------------------------------------

		::

		+-----------+
		\| ML cap #0 \|
		+-----------+
		\| ML cap #1 \|
		+-----------+
		\| ML cap #2 \|---+
		+-----------+ \|
		\|
		+--> 0x0 +---------------+ LCAP
		\| ALT=1 \|
		+---------------+
		\| INTC \|
		+---------------+
		\| OFLS \|
		+---------------+
		\| SLCOUNT=3 \|-------------------------for each sublink x -------------------------+
		+---------------+ \|
		\|
		0x4 +---------------+ LCTL \|
		\| INTSTS \| \|
		+---------------+ \|
		\| CPA (x bits) \| \|
		+---------------+ \|
		\| SPA (x bits) \| \|
		+---------------+ \|
		\| INTEN \| \|
		+---------------+ \|
		\| OFLEN \| \|
		+---------------+ +---> 0x28000 +-----------------+ 0x00028000 \|
		\| \| SSP SHIM \| \|
		0x8 +---------------+ LOSIDV \| \| generic \| \|
		\| L1OSIVD15 \| \| +-----------------+ 0x00028100 \|
		+---------------+ \| \| SSP IP \| \|
		\| L1OSIDV.. \| \| +-----------------+ 0x00028C00 \|
		+---------------+ \| \| SSP SHIM \| \|
		\| L1OSIDV1 \| \| \| vendor-specific \| \|
		+---------------+ \| +-----------------+ \|
		\| v
		0x20 +---------------+ LEPTR \| +-----------------+ 0x00028000 + 0x1000 * x
		\| ID = 0xC0 \| \| \| SSP SHIM \|
		+---------------+ \| \| generic \|
		\| VER \| \| +-----------------+ 0x00028100 + 0x1000 * x
		+---------------+ \| \| SSP IP \|
		\| PTR \|-----------+ +-----------------+ 0x00028C00 + 0x1000 * x
		+---------------+ \| SSP SHIM \|
		\| vendor-specific \|
		+-----------------+

include/sound/hda-mlink.h

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		/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
		/*
		* This file is provided under a dual BSD/GPLv2 license. When using or
		* redistributing this file, you may do so under either license.
		*
		* Copyright(c) 2022-2023 Intel Corporation. All rights reserved.
		*/

		struct hdac_bus;
		struct hdac_ext_link;

		#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_MLINK)

		int hda_bus_ml_init(struct hdac_bus *bus);
		void hda_bus_ml_free(struct hdac_bus *bus);

		int hdac_bus_eml_get_count(struct hdac_bus *bus, bool alt, int elid);
		void hdac_bus_eml_enable_interrupt(struct hdac_bus *bus, bool alt, int elid, bool enable);
		bool hdac_bus_eml_check_interrupt(struct hdac_bus *bus, bool alt, int elid);

		int hdac_bus_eml_set_syncprd_unlocked(struct hdac_bus *bus, bool alt, int elid, u32 syncprd);
		int hdac_bus_eml_sdw_set_syncprd_unlocked(struct hdac_bus *bus, u32 syncprd);

		int hdac_bus_eml_wait_syncpu_unlocked(struct hdac_bus *bus, bool alt, int elid);
		int hdac_bus_eml_sdw_wait_syncpu_unlocked(struct hdac_bus *bus);

		void hdac_bus_eml_sync_arm_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink);
		void hdac_bus_eml_sdw_sync_arm_unlocked(struct hdac_bus *bus, int sublink);

		int hdac_bus_eml_sync_go_unlocked(struct hdac_bus *bus, bool alt, int elid);
		int hdac_bus_eml_sdw_sync_go_unlocked(struct hdac_bus *bus);

		bool hdac_bus_eml_check_cmdsync_unlocked(struct hdac_bus *bus, bool alt, int elid);
		bool hdac_bus_eml_sdw_check_cmdsync_unlocked(struct hdac_bus *bus);

		int hdac_bus_eml_power_up(struct hdac_bus *bus, bool alt, int elid, int sublink);
		int hdac_bus_eml_power_up_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink);

		int hdac_bus_eml_power_down(struct hdac_bus *bus, bool alt, int elid, int sublink);
		int hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink);

		int hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink);
		int hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink);

		int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num);

		void hda_bus_ml_put_all(struct hdac_bus *bus);
		void hda_bus_ml_reset_losidv(struct hdac_bus *bus);
		int hda_bus_ml_resume(struct hdac_bus *bus);
		int hda_bus_ml_suspend(struct hdac_bus *bus);

		struct hdac_ext_link hdac_bus_eml_ssp_get_hlink(struct hdac_bus bus);
		struct hdac_ext_link hdac_bus_eml_dmic_get_hlink(struct hdac_bus bus);

		struct mutex hdac_bus_eml_get_mutex(struct hdac_bus bus, bool alt, int elid);

		int hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable);

		#else

		static inline int
		hda_bus_ml_init(struct hdac_bus *bus) { return 0; }

		static inline void hda_bus_ml_free(struct hdac_bus *bus) { }

		static inline int
		hdac_bus_eml_get_count(struct hdac_bus *bus, bool alt, int elid) { return 0; }

		static inline void
		hdac_bus_eml_enable_interrupt(struct hdac_bus *bus, bool alt, int elid, bool enable) { }

		static inline bool
		hdac_bus_eml_check_interrupt(struct hdac_bus *bus, bool alt, int elid) { return false; }

		static inline int
		hdac_bus_eml_set_syncprd_unlocked(struct hdac_bus *bus, bool alt, int elid, u32 syncprd)
		{
		return 0;
		}

		static inline int
		hdac_bus_eml_sdw_set_syncprd_unlocked(struct hdac_bus *bus, u32 syncprd)
		{
		return 0;
		}

		static inline int
		hdac_bus_eml_wait_syncpu_unlocked(struct hdac_bus *bus, bool alt, int elid)
		{
		return 0;
		}

		static inline int
		hdac_bus_eml_sdw_wait_syncpu_unlocked(struct hdac_bus *bus) { return 0; }

		static inline void
		hdac_bus_eml_sync_arm_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink) { }

		static inline void
		hdac_bus_eml_sdw_sync_arm_unlocked(struct hdac_bus *bus, int sublink) { }

		static inline int
		hdac_bus_eml_sync_go_unlocked(struct hdac_bus *bus, bool alt, int elid) { return 0; }

		static inline int
		hdac_bus_eml_sdw_sync_go_unlocked(struct hdac_bus *bus) { return 0; }

		static inline bool
		hdac_bus_eml_check_cmdsync_unlocked(struct hdac_bus *bus, bool alt, int elid) { return false; }

		static inline bool
		hdac_bus_eml_sdw_check_cmdsync_unlocked(struct hdac_bus *bus) { return false; }

		static inline int
		hdac_bus_eml_power_up(struct hdac_bus *bus, bool alt, int elid, int sublink)
		{
		return 0;
		}

		static inline int
		hdac_bus_eml_power_up_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink)
		{
		return 0;
		}

		static inline int
		hdac_bus_eml_power_down(struct hdac_bus *bus, bool alt, int elid, int sublink)
		{
		return 0;
		}

		static inline int
		hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink)
		{
		return 0;
		}

		static inline int
		hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink) { return 0; }

		static inline int
		hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink) { return 0; }

		static inline int
		hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num) { return 0; }

		static inline void hda_bus_ml_put_all(struct hdac_bus *bus) { }
		static inline void hda_bus_ml_reset_losidv(struct hdac_bus *bus) { }
		static inline int hda_bus_ml_resume(struct hdac_bus *bus) { return 0; }
		static inline int hda_bus_ml_suspend(struct hdac_bus *bus) { return 0; }

		static inline struct hdac_ext_link *
		hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus) { return NULL; }

		static inline struct hdac_ext_link *
		hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus) { return NULL; }

		static inline struct mutex *
		hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid) { return NULL; }

		static inline int
		hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable)
		{
		return 0;
		}
		#endif /* CONFIG_SND_SOC_SOF_HDA */

include/sound/hda_register.h

+38 −2

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		@@ -258,14 +258,27 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
		#define AZX_ML_BASE 0x40
		#define AZX_ML_INTERVAL 0x40

		/* HDaudio registers valid for HDaudio and HDaudio extended links */
		#define AZX_REG_ML_LCAP 0x00
		#define AZX_REG_ML_LCTL 0x04

		#define AZX_ML_HDA_LCAP_ALT BIT(28)
		#define AZX_ML_HDA_LCAP_ALT_HDA 0x0
		#define AZX_ML_HDA_LCAP_ALT_HDA_EXT 0x1

		#define AZX_ML_HDA_LCAP_INTC BIT(27) /* only used if ALT == 1 */
		#define AZX_ML_HDA_LCAP_OFLS BIT(26) /* only used if ALT == 1 */
		#define AZX_ML_HDA_LCAP_LSS BIT(23) /* only used if ALT == 1 */
		#define AZX_ML_HDA_LCAP_SLCOUNT GENMASK(22, 20) /* only used if ALT == 1 */

		#define AZX_REG_ML_LCTL 0x04
		#define AZX_ML_LCTL_INTSTS BIT(31) /* only used if ALT == 1 */
		#define AZX_ML_LCTL_CPA BIT(23)
		#define AZX_ML_LCTL_CPA_SHIFT 23
		#define AZX_ML_LCTL_SPA BIT(16)
		#define AZX_ML_LCTL_SPA_SHIFT 16
		#define AZX_ML_LCTL_SCF GENMASK(3, 0)
		#define AZX_ML_LCTL_INTEN BIT(5) /* only used if ALT == 1 */
		#define AZX_ML_LCTL_OFLEN BIT(4) /* only used if ALT == 1 */
		#define AZX_ML_LCTL_SCF GENMASK(3, 0) /* only used if ALT == 0 */

		#define AZX_REG_ML_LOSIDV 0x08

		@@ -273,12 +286,35 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
		#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE

		#define AZX_REG_ML_LSDIID 0x0C
		#define AZX_REG_ML_LSDIID_OFFSET(x) (0x0C + (x) * 0x02) /* only used if ALT == 1 */

		/* HDaudio registers only valid if LCAP.ALT == 0 */
		#define AZX_REG_ML_LPSOO 0x10
		#define AZX_REG_ML_LPSIO 0x12
		#define AZX_REG_ML_LWALFC 0x18
		#define AZX_REG_ML_LOUTPAY 0x20
		#define AZX_REG_ML_LINPAY 0x30

		/* HDaudio Extended link registers only valid if LCAP.ALT == 1 */
		#define AZX_REG_ML_LSYNC 0x1C

		#define AZX_REG_ML_LSYNC_CMDSYNC BIT(24)
		#define AZX_REG_ML_LSYNC_CMDSYNC_SHIFT 24
		#define AZX_REG_ML_LSYNC_SYNCGO BIT(23)
		#define AZX_REG_ML_LSYNC_SYNCPU BIT(20)
		#define AZX_REG_ML_LSYNC_SYNCPRD GENMASK(19, 0)

		#define AZX_REG_ML_LEPTR 0x20

		#define AZX_REG_ML_LEPTR_ID GENMASK(31, 24)
		#define AZX_REG_ML_LEPTR_ID_SHIFT 24
		#define AZX_REG_ML_LEPTR_ID_SDW 0x00
		#define AZX_REG_ML_LEPTR_ID_INTEL_SSP 0xC0
		#define AZX_REG_ML_LEPTR_ID_INTEL_DMIC 0xC1
		#define AZX_REG_ML_LEPTR_ID_INTEL_UAOL 0xC2
		#define AZX_REG_ML_LEPTR_VER GENMASK(23, 20)
		#define AZX_REG_ML_LEPTR_PTR GENMASK(19, 0)

		/* registers for DMA Resume Capability Structure */
		#define AZX_DRSM_CAP_ID 0x5
		#define AZX_REG_DRSM_CTL 0x4

sound/soc/sof/intel/Kconfig

+7 −0

Original line number	Diff line number	Diff line
		@@ -269,6 +269,13 @@ config SND_SOC_SOF_HDA_COMMON
		select SND_INTEL_DSP_CONFIG
		select SND_SOC_SOF_HDA_LINK_BASELINE
		select SND_SOC_SOF_HDA_PROBES
		select SND_SOC_SOF_HDA_MLINK if SND_SOC_SOF_HDA_LINK
		help
		This option is not user-selectable but automagically handled by
		'select' statements at a higher level.

		config SND_SOC_SOF_HDA_MLINK
		tristate
		help
		This option is not user-selectable but automagically handled by
		'select' statements at a higher level.