Commit a1fb410a authored by Marek Behún's avatar Marek Behún Committed by David S. Miller
Browse files

phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r 



Add support for PHY_INTERFACE_MODE_5GBASER mode within the Marvell CP110
common PHY driver.

This is currently only supported via SMC calls to TF-A. Legacy support
may be added later, if needed.

Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 75e47206

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

+9 −0
Original line number Diff line number Diff line
@@ -141,6 +141,7 @@ 
#define COMPHY_FW_SPEED_1250	0

#define COMPHY_FW_SPEED_3125	2

#define COMPHY_FW_SPEED_5000	3

#define COMPHY_FW_SPEED_515625	4

#define COMPHY_FW_SPEED_103125	6

#define COMPHY_FW_PORT_OFFSET	8

#define COMPHY_FW_PORT_MASK	GENMASK(11, 8)
@@ -220,6 +221,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_5GBASER, 0x1, COMPHY_FW_MODE_XFI),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),

	GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),

	GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
@@ -234,6 +236,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	/* lane 4 */

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_2500BASEX),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_5GBASER, 0x2, COMPHY_FW_MODE_XFI),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),

	GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
@@ -241,6 +244,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_2500BASEX),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, -1, COMPHY_FW_MODE_XFI),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),

	/* lane 5 */

	ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
@@ -790,6 +794,11 @@ static int mvebu_comphy_power_on(struct phy *phy) 
				lane->id);

			fw_speed = COMPHY_FW_SPEED_3125;

			break;

		case PHY_INTERFACE_MODE_5GBASER:

			dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",

				lane->id);

			fw_speed = COMPHY_FW_SPEED_515625;

			break;

		case PHY_INTERFACE_MODE_10GBASER:

			dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",

				lane->id);