Commit a2e87e9e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: use MDSS data for programming SSPP 



Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects
the hardware register values.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/550054/
Link: https://lore.kernel.org/r/20230728213320.97309-6-dmitry.baryshkov@linaro.org
parent 6f410b24

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

+10 −8
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ 
#include "dpu_hw_sspp.h"

#include "dpu_kms.h"



#include "msm_mdss.h"



#include <drm/drm_file.h>



#define DPU_FETCH_CONFIG_RESET_VALUE   0x00000087
@@ -270,26 +272,26 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, 
		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,

			DPU_FETCH_CONFIG_RESET_VALUE |

			ctx->ubwc->highest_bank_bit << 18);

		switch (ctx->ubwc->ubwc_version) {

		case DPU_HW_UBWC_VER_10:

		switch (ctx->ubwc->ubwc_enc_version) {

		case UBWC_1_0:

			fast_clear = fmt->alpha_enable ? BIT(31) : 0;

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

					fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |

					BIT(8) |

					(ctx->ubwc->highest_bank_bit << 4));

			break;

		case DPU_HW_UBWC_VER_20:

		case UBWC_2_0:

			fast_clear = fmt->alpha_enable ? BIT(31) : 0;

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

					fast_clear | (ctx->ubwc->ubwc_swizzle) |

					(ctx->ubwc->highest_bank_bit << 4));

			break;

		case DPU_HW_UBWC_VER_30:

		case UBWC_3_0:

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

					BIT(30) | (ctx->ubwc->ubwc_swizzle) |

					(ctx->ubwc->highest_bank_bit << 4));

			break;

		case DPU_HW_UBWC_VER_40:

		case UBWC_4_0:

			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

					DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));

			break;
@@ -670,11 +672,11 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, 
#endif



struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,

		void __iomem *addr, const struct dpu_ubwc_cfg *ubwc)

		void __iomem *addr, const struct msm_mdss_data *mdss_data)

{

	struct dpu_hw_sspp *hw_pipe;



	if (!addr || !ubwc)

	if (!addr)

		return ERR_PTR(-EINVAL);



	hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
@@ -685,7 +687,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, 
	hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP;



	/* Assign ops */

	hw_pipe->ubwc = ubwc;

	hw_pipe->ubwc = mdss_data;

	hw_pipe->idx = cfg->id;

	hw_pipe->cap = cfg;

	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

+3 −3
Original line number Diff line number Diff line
@@ -317,7 +317,7 @@ struct dpu_hw_sspp_ops { 
struct dpu_hw_sspp {

	struct dpu_hw_blk base;

	struct dpu_hw_blk_reg_map hw;

	const struct dpu_ubwc_cfg *ubwc;

	const struct msm_mdss_data *ubwc;



	/* Pipe */

	enum dpu_sspp idx;
@@ -333,10 +333,10 @@ struct dpu_kms; 
 * Should be called once before accessing every pipe.

 * @cfg:  Pipe catalog entry for which driver object is required

 * @addr: Mapped register io address of MDP

 * @ubwc: UBWC configuration data

 * @mdss_data: UBWC / MDSS configuration data

 */

struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,

		void __iomem *addr, const struct dpu_ubwc_cfg *ubwc);

		void __iomem *addr, const struct msm_mdss_data *mdss_data);



/**

 * dpu_hw_sspp_destroy(): Destroys SSPP driver context

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

+15 −1
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 


#include "msm_drv.h"

#include "msm_mmu.h"

#include "msm_mdss.h"

#include "msm_gem.h"

#include "disp/msm_disp_snapshot.h"
@@ -1124,7 +1125,20 @@ static int dpu_kms_hw_init(struct msm_kms *kms) 
		goto power_error;

	}



	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);

	dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent);

	if (IS_ERR(dpu_kms->mdss)) {

		rc = PTR_ERR(dpu_kms->mdss);

		DPU_ERROR("failed to get MDSS data: %d\n", rc);

		goto power_error;

	}



	if (!dpu_kms->mdss) {

		rc = -EINVAL;

		DPU_ERROR("NULL MDSS data\n");

		goto power_error;

	}



	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio);

	if (rc) {

		DPU_ERROR("rm init failed: %d\n", rc);

		goto power_error;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ struct dpu_kms { 
	struct msm_kms base;

	struct drm_device *dev;

	const struct dpu_mdss_cfg *catalog;

	const struct msm_mdss_data *mdss;



	/* io/register spaces: */

	void __iomem *mmio, *vbif[VBIF_MAX];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

+2 −1
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ int dpu_rm_destroy(struct dpu_rm *rm) 


int dpu_rm_init(struct dpu_rm *rm,

		const struct dpu_mdss_cfg *cat,

		const struct msm_mdss_data *mdss_data,

		void __iomem *mmio)

{

	int rc, i;
@@ -230,7 +231,7 @@ int dpu_rm_init(struct dpu_rm *rm, 
		struct dpu_hw_sspp *hw;

		const struct dpu_sspp_cfg *sspp = &cat->sspp[i];



		hw = dpu_hw_sspp_init(sspp, mmio, cat->ubwc);

		hw = dpu_hw_sspp_init(sspp, mmio, mdss_data);

		if (IS_ERR(hw)) {

			rc = PTR_ERR(hw);

			DPU_ERROR("failed sspp object creation: err %d\n", rc);