Commit a6a6cb34 authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Move OPP to stream_res



find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/pipes->opp/pipes->stream_res\.opp/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/ctx->opp->/ctx->stream_res\.opp->/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/pipe->opp/pipe->stream_res\.opp/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/pipe_ctx->opp/pipe_ctx->stream_res\.opp/g'

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 86a66c4e
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+2 −2
Original line number Diff line number Diff line
@@ -365,8 +365,8 @@ void set_dither_option(struct dc_stream_state *stream,
	resource_build_bit_depth_reduction_params(stream,
				&params);
	stream->bit_depth_params = params;
	pipes->opp->funcs->
		opp_program_bit_depth_reduction(pipes->opp, &params);
	pipes->stream_res.opp->funcs->
		opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
}

static void allocate_dc_stream_funcs(struct core_dc *core_dc)
+4 −4
Original line number Diff line number Diff line
@@ -2372,8 +2372,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
	{
		/* disable bit depth reduction */
		pipe_ctx->stream->bit_depth_params = params;
		pipe_ctx->opp->funcs->
			opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
		pipe_ctx->stream_res.opp->funcs->
			opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);

		pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
				controller_test_pattern, color_depth);
@@ -2385,8 +2385,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
		resource_build_bit_depth_reduction_params(pipe_ctx->stream,
					&params);
		pipe_ctx->stream->bit_depth_params = params;
		pipe_ctx->opp->funcs->
			opp_program_bit_depth_reduction(pipe_ctx->opp, &params);
		pipe_ctx->stream_res.opp->funcs->
			opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);

		pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+3 −3
Original line number Diff line number Diff line
@@ -1015,7 +1015,7 @@ static int acquire_first_split_pipe(
			pipe_ctx->plane_res.mi = pool->mis[i];
			pipe_ctx->plane_res.ipp = pool->ipps[i];
			pipe_ctx->plane_res.xfm = pool->transforms[i];
			pipe_ctx->opp = pool->opps[i];
			pipe_ctx->stream_res.opp = pool->opps[i];
			pipe_ctx->dis_clk = pool->display_clock;
			pipe_ctx->pipe_idx = i;

@@ -1095,7 +1095,7 @@ bool resource_attach_surfaces_to_context(

		if (tail_pipe) {
			free_pipe->tg = tail_pipe->tg;
			free_pipe->opp = tail_pipe->opp;
			free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
			free_pipe->stream_enc = tail_pipe->stream_enc;
			free_pipe->audio = tail_pipe->audio;
			free_pipe->clock_source = tail_pipe->clock_source;
@@ -1245,7 +1245,7 @@ static int acquire_first_free_pipe(
			pipe_ctx->plane_res.mi = pool->mis[i];
			pipe_ctx->plane_res.ipp = pool->ipps[i];
			pipe_ctx->plane_res.xfm = pool->transforms[i];
			pipe_ctx->opp = pool->opps[i];
			pipe_ctx->stream_res.opp = pool->opps[i];
			pipe_ctx->dis_clk = pool->display_clock;
			pipe_ctx->pipe_idx = i;

+6 −6
Original line number Diff line number Diff line
@@ -1044,16 +1044,16 @@ static enum dc_status apply_single_controller_ctx_to_hw(
	/*  */
	dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);

	pipe_ctx->opp->funcs->opp_set_dyn_expansion(
			pipe_ctx->opp,
	pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
			pipe_ctx->stream_res.opp,
			COLOR_SPACE_YCBCR601,
			stream->timing.display_color_depth,
			pipe_ctx->stream->signal);

	/* FPGA does not program backend */
	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
	pipe_ctx->opp->funcs->opp_program_fmt(
			pipe_ctx->opp,
	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
			pipe_ctx->stream_res.opp,
			&stream->bit_depth_params,
			&stream->clamping);
		return DC_OK;
@@ -1078,8 +1078,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(


/*vbios crtc_source_selection and encoder_setup will override fmt_C*/
	pipe_ctx->opp->funcs->opp_program_fmt(
			pipe_ctx->opp,
	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
			pipe_ctx->stream_res.opp,
			&stream->bit_depth_params,
			&stream->clamping);

+1 −1
Original line number Diff line number Diff line
@@ -1020,7 +1020,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
	pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
	/*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
	pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
	pipe_ctx->opp = pool->opps[underlay_idx];
	pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
	pipe_ctx->dis_clk = pool->display_clock;
	pipe_ctx->pipe_idx = underlay_idx;

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