Commit a72848e8 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: msm8998: Disable some components by default



Some components (like PCIe) are not used on all devices and
with a certain firmware configuration they might end up triggering
a force reboot or a Synchronous Abort.

This commit brings no functional difference as the nodes are
enabled on devices which didn't disable them previously.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-6-konrad.dybcio@somainline.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent c43cfc54
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+16 −0
Original line number Diff line number Diff line
@@ -74,6 +74,14 @@ &CPU7 {
	cpu-idle-states = <&BIG_CPU_SLEEP_1>;
};

&pcie0 {
	status = "okay";
};

&pcie_phy {
	status = "okay";
};

&pm8005_lsid1 {
	pm8005-regulators {
		compatible = "qcom,pm8005-regulators";
@@ -295,6 +303,14 @@ &sdhc2 {
	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
};

&ufshc {
	status = "okay";
};

&ufsphy {
	status = "okay";
};

&usb3 {
	status = "okay";
};
+10 −0
Original line number Diff line number Diff line
@@ -106,6 +106,14 @@ &funnel5 {
	// status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie_phy {
	status = "okay";
};

&pm8005_lsid1 {
	pm8005-regulators {
		compatible = "qcom,pm8005-regulators";
@@ -345,6 +353,7 @@ &stm {
};

&ufshc {
	status = "okay";
	vcc-supply = <&vreg_l20a_2p95>;
	vccq-supply = <&vreg_l26a_1p2>;
	vccq2-supply = <&vreg_s4a_1p8>;
@@ -354,6 +363,7 @@ &ufshc {
};

&ufsphy {
	status = "okay";
	vdda-phy-supply = <&vreg_l1a_0p875>;
	vdda-pll-supply = <&vreg_l2a_1p2>;
	vddp-ref-clk-supply = <&vreg_l26a_1p2>;
+5 −1
Original line number Diff line number Diff line
@@ -945,6 +945,7 @@ pcie0: pci@1c00000 {
			num-lanes = <1>;
			phys = <&pciephy>;
			phy-names = "pciephy";
			status = "disabled";

			ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
@@ -970,11 +971,12 @@ pcie0: pci@1c00000 {
			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
		};

		phy@1c06000 {
		pcie_phy: phy@1c06000 {
			compatible = "qcom,msm8998-qmp-pcie-phy";
			reg = <0x01c06000 0x18c>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
			ranges;

			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
@@ -1007,6 +1009,7 @@ ufshc: ufshc@1da4000 {
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			power-domains = <&gcc UFS_GDSC>;
			status = "disabled";
			#reset-cells = <1>;

			clock-names =
@@ -1046,6 +1049,7 @@ ufsphy: phy@1da7000 {
			reg = <0x01da7000 0x18c>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
			ranges;

			clock-names =