Commit a76087cf authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn3.0: add software ring share memory support 



Support software ring share memory with vcn firmware.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 52f9535c

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+31 −4
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ static int vcn_v3_0_sw_init(void *handle) 
	}



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		volatile struct amdgpu_fw_shared *fw_shared;

		if (adev->vcn.harvest_config & (1 << i))

			continue;
@@ -234,6 +235,10 @@ static int vcn_v3_0_sw_init(void *handle) 
			if (r)

				return r;

		}



		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;

		fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG);

		fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);

	}



	if (amdgpu_sriov_vf(adev)) {
@@ -257,7 +262,17 @@ static int vcn_v3_0_sw_init(void *handle) 
static int vcn_v3_0_sw_fini(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int r;

	int i, r;



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		volatile struct amdgpu_fw_shared *fw_shared;



		if (adev->vcn.harvest_config & (1 << i))

			continue;

		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;

		fw_shared->present_flag_0 = 0;

		fw_shared->sw_ring.is_enabled = false;

	}



	if (amdgpu_sriov_vf(adev))

		amdgpu_virt_free_mm_table(adev);
@@ -467,6 +482,15 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 
		upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);

	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);



	/* non-cache window */

	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

		lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));

	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,

		upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));

	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);

	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));

}



static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
@@ -549,13 +573,16 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 


	/* non-cache window */

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);

			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);

			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),

			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);

			VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),

			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);

}



static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)