Commit a7e660e5 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: expose the firmware_capability from firmware_info table 



That will help to determine whether 2ND_USB20_PORT workaround is
needed for Sienna Cichlid.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ac7804bb

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

+1 −0
Original line number Diff line number Diff line
@@ -227,6 +227,7 @@ struct smu_bios_boot_up_values 
	uint32_t			content_revision;

	uint32_t			fclk;

	uint32_t			lclk;

	uint32_t			firmware_caps;

};



enum smu_table_id

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

+2 −0
Original line number Diff line number Diff line
@@ -554,6 +554,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) 
		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;

		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;

		smu->smu_table.boot_values.pp_table_id = 0;

		smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;

		break;

	case 3:

	default:
@@ -569,6 +570,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) 
		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;

		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;

		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;

		smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;

	}



	smu->smu_table.boot_values.format_revision = header->format_revision;