Commit a7fc833e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp: move QSERDES V3 registers to separate headers 



Move QSERDES V3 registers to the separate headers.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-10-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9e1bae6d

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_

#define QCOM_PHY_QMP_QSERDES_COM_V3_H_



/* Only for QMP V3 PHY - QSERDES COM registers */

#define QSERDES_V3_COM_ATB_SEL1				0x000

#define QSERDES_V3_COM_ATB_SEL2				0x004

#define QSERDES_V3_COM_FREQ_UPDATE			0x008

#define QSERDES_V3_COM_BG_TIMER				0x00c

#define QSERDES_V3_COM_SSC_EN_CENTER			0x010

#define QSERDES_V3_COM_SSC_ADJ_PER1			0x014

#define QSERDES_V3_COM_SSC_ADJ_PER2			0x018

#define QSERDES_V3_COM_SSC_PER1				0x01c

#define QSERDES_V3_COM_SSC_PER2				0x020

#define QSERDES_V3_COM_SSC_STEP_SIZE1			0x024

#define QSERDES_V3_COM_SSC_STEP_SIZE2			0x028

#define QSERDES_V3_COM_POST_DIV				0x02c

#define QSERDES_V3_COM_POST_DIV_MUX			0x030

#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN		0x034

#define QSERDES_V3_COM_CLK_ENABLE1			0x038

#define QSERDES_V3_COM_SYS_CLK_CTRL			0x03c

#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE		0x040

#define QSERDES_V3_COM_PLL_EN				0x044

#define QSERDES_V3_COM_PLL_IVCO				0x048

#define QSERDES_V3_COM_CLK_EP_DIV			0x05c

#define QSERDES_V3_COM_CP_CTRL_MODE0			0x060

#define QSERDES_V3_COM_CP_CTRL_MODE1			0x064

#define QSERDES_V3_COM_PLL_RCTRL_MODE0			0x068

#define QSERDES_V3_COM_PLL_RCTRL_MODE1			0x06c

#define QSERDES_V3_COM_PLL_CCTRL_MODE0			0x070

#define QSERDES_V3_COM_PLL_CCTRL_MODE1			0x074

#define QSERDES_V3_COM_SYSCLK_EN_SEL			0x080

#define QSERDES_V3_COM_RESETSM_CNTRL			0x088

#define QSERDES_V3_COM_RESETSM_CNTRL2			0x08c

#define QSERDES_V3_COM_LOCK_CMP_EN			0x090

#define QSERDES_V3_COM_LOCK_CMP_CFG			0x094

#define QSERDES_V3_COM_LOCK_CMP1_MODE0			0x098

#define QSERDES_V3_COM_LOCK_CMP2_MODE0			0x09c

#define QSERDES_V3_COM_LOCK_CMP3_MODE0			0x0a0

#define QSERDES_V3_COM_LOCK_CMP1_MODE1			0x0a4

#define QSERDES_V3_COM_LOCK_CMP2_MODE1			0x0a8

#define QSERDES_V3_COM_LOCK_CMP3_MODE1			0x0ac

#define QSERDES_V3_COM_DEC_START_MODE0			0x0b0

#define QSERDES_V3_COM_DEC_START_MODE1			0x0b4

#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0		0x0b8

#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0		0x0bc

#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0		0x0c0

#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1		0x0c4

#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1		0x0c8

#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1		0x0cc

#define QSERDES_V3_COM_INTEGLOOP_INITVAL		0x0d0

#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0		0x0d8

#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0		0x0dc

#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1		0x0e0

#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1		0x0e4

#define QSERDES_V3_COM_VCO_TUNE_CTRL			0x0ec

#define QSERDES_V3_COM_VCO_TUNE_MAP			0x0f0

#define QSERDES_V3_COM_VCO_TUNE1_MODE0			0x0f4

#define QSERDES_V3_COM_VCO_TUNE2_MODE0			0x0f8

#define QSERDES_V3_COM_VCO_TUNE1_MODE1			0x0fc

#define QSERDES_V3_COM_VCO_TUNE2_MODE1			0x100

#define QSERDES_V3_COM_VCO_TUNE_INITVAL1		0x104

#define QSERDES_V3_COM_VCO_TUNE_INITVAL2		0x108

#define QSERDES_V3_COM_VCO_TUNE_TIMER1			0x11c

#define QSERDES_V3_COM_VCO_TUNE_TIMER2			0x120

#define QSERDES_V3_COM_CLK_SELECT			0x138

#define QSERDES_V3_COM_HSCLK_SEL			0x13c

#define QSERDES_V3_COM_CORECLK_DIV_MODE0		0x148

#define QSERDES_V3_COM_CORECLK_DIV_MODE1		0x14c

#define QSERDES_V3_COM_CORE_CLK_EN			0x154

#define QSERDES_V3_COM_C_READY_STATUS			0x158

#define QSERDES_V3_COM_CMN_CONFIG			0x15c

#define QSERDES_V3_COM_SVS_MODE_CLK_SEL			0x164

#define QSERDES_V3_COM_DEBUG_BUS0			0x168

#define QSERDES_V3_COM_DEBUG_BUS1			0x16c

#define QSERDES_V3_COM_DEBUG_BUS2			0x170

#define QSERDES_V3_COM_DEBUG_BUS3			0x174

#define QSERDES_V3_COM_DEBUG_BUS_SEL			0x178

#define QSERDES_V3_COM_CMN_MODE				0x184



#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_

#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_



/* Only for QMP V3 PHY - TX registers */

#define QSERDES_V3_TX_BIST_MODE_LANENO			0x000

#define QSERDES_V3_TX_CLKBUF_ENABLE			0x008

#define QSERDES_V3_TX_TX_EMP_POST1_LVL			0x00c

#define QSERDES_V3_TX_TX_DRV_LVL			0x01c

#define QSERDES_V3_TX_RESET_TSYNC_EN			0x024

#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN		0x028

#define QSERDES_V3_TX_TX_BAND				0x02c

#define QSERDES_V3_TX_SLEW_CNTL				0x030

#define QSERDES_V3_TX_INTERFACE_SELECT			0x034

#define QSERDES_V3_TX_RES_CODE_LANE_TX			0x03c

#define QSERDES_V3_TX_RES_CODE_LANE_RX			0x040

#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX		0x044

#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX		0x048

#define QSERDES_V3_TX_DEBUG_BUS_SEL			0x058

#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN		0x05c

#define QSERDES_V3_TX_HIGHZ_DRVR_EN			0x060

#define QSERDES_V3_TX_TX_POL_INV			0x064

#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN	0x068

#define QSERDES_V3_TX_LANE_MODE_1			0x08c

#define QSERDES_V3_TX_RCV_DETECT_LVL_2			0x0a4

#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN			0x0c0

#define QSERDES_V3_TX_TX_INTERFACE_MODE			0x0c4

#define QSERDES_V3_TX_VMODE_CTRL1			0x0f0



/* Only for QMP V3 PHY - RX registers */

#define QSERDES_V3_RX_UCDR_FO_GAIN			0x008

#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF			0x00c

#define QSERDES_V3_RX_UCDR_SO_GAIN			0x014

#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF		0x024

#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER		0x028

#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN			0x02c

#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN		0x030

#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034

#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c

#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040

#define QSERDES_V3_RX_UCDR_PI_CONTROLS			0x044

#define QSERDES_V3_RX_RX_TERM_BW			0x07c

#define QSERDES_V3_RX_VGA_CAL_CNTRL1			0x0bc

#define QSERDES_V3_RX_VGA_CAL_CNTRL2			0x0c0

#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB			0x0c8

#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB			0x0cc

#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2		0x0d4

#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3		0x0d8

#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4		0x0dc

#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x0f8

#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x0fc

#define QSERDES_V3_RX_SIGDET_ENABLES			0x100

#define QSERDES_V3_RX_SIGDET_CNTRL			0x104

#define QSERDES_V3_RX_SIGDET_LVL			0x108

#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL		0x10c

#define QSERDES_V3_RX_RX_BAND				0x110

#define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c

#define QSERDES_V3_RX_RX_MODE_00			0x164

#define QSERDES_V3_RX_RX_MODE_01			0x168



#endif

drivers/phy/qualcomm/phy-qcom-qmp.h

+5 −133
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@@ -9,6 +9,9 @@ 
#include "phy-qcom-qmp-qserdes-com.h"

#include "phy-qcom-qmp-qserdes-txrx.h"



#include "phy-qcom-qmp-qserdes-com-v3.h"

#include "phy-qcom-qmp-qserdes-txrx-v3.h"



/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */



#define QSERDES_PLL_BG_TIMER				0x00c
@@ -105,21 +108,7 @@ 
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL			0x14

#define QPHY_V3_DP_COM_RESET_OVRD_CTRL			0x1c



/* Only for QMP V3 PHY - QSERDES COM registers */

#define QSERDES_V3_COM_ATB_SEL1				0x000

#define QSERDES_V3_COM_ATB_SEL2				0x004

#define QSERDES_V3_COM_FREQ_UPDATE			0x008

#define QSERDES_V3_COM_BG_TIMER				0x00c

#define QSERDES_V3_COM_SSC_EN_CENTER			0x010

#define QSERDES_V3_COM_SSC_ADJ_PER1			0x014

#define QSERDES_V3_COM_SSC_ADJ_PER2			0x018

#define QSERDES_V3_COM_SSC_PER1				0x01c

#define QSERDES_V3_COM_SSC_PER2				0x020

#define QSERDES_V3_COM_SSC_STEP_SIZE1			0x024

#define QSERDES_V3_COM_SSC_STEP_SIZE2			0x028

#define QSERDES_V3_COM_POST_DIV				0x02c

#define QSERDES_V3_COM_POST_DIV_MUX			0x030

#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN		0x034

/* QSERDES V3 COM bits */

# define QSERDES_V3_COM_BIAS_EN				0x0001

# define QSERDES_V3_COM_BIAS_EN_MUX			0x0002

# define QSERDES_V3_COM_CLKBUF_R_EN			0x0004
@@ -127,130 +116,13 @@ 
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL		0x0010

# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L		0x0020

# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R		0x0040

#define QSERDES_V3_COM_CLK_ENABLE1			0x038

#define QSERDES_V3_COM_SYS_CLK_CTRL			0x03c

#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE		0x040

#define QSERDES_V3_COM_PLL_EN				0x044

#define QSERDES_V3_COM_PLL_IVCO				0x048

#define QSERDES_V3_COM_LOCK_CMP1_MODE0			0x098

#define QSERDES_V3_COM_LOCK_CMP2_MODE0			0x09c

#define QSERDES_V3_COM_LOCK_CMP3_MODE0			0x0a0

#define QSERDES_V3_COM_LOCK_CMP1_MODE1			0x0a4

#define QSERDES_V3_COM_LOCK_CMP2_MODE1			0x0a8

#define QSERDES_V3_COM_LOCK_CMP3_MODE1			0x0ac

#define QSERDES_V3_COM_CLK_EP_DIV			0x05c

#define QSERDES_V3_COM_CP_CTRL_MODE0			0x060

#define QSERDES_V3_COM_CP_CTRL_MODE1			0x064

#define QSERDES_V3_COM_PLL_RCTRL_MODE0			0x068

#define QSERDES_V3_COM_PLL_RCTRL_MODE1			0x06c

#define QSERDES_V3_COM_PLL_CCTRL_MODE0			0x070

#define QSERDES_V3_COM_PLL_CCTRL_MODE1			0x074

#define QSERDES_V3_COM_SYSCLK_EN_SEL			0x080

#define QSERDES_V3_COM_RESETSM_CNTRL			0x088

#define QSERDES_V3_COM_RESETSM_CNTRL2			0x08c

#define QSERDES_V3_COM_LOCK_CMP_EN			0x090

#define QSERDES_V3_COM_LOCK_CMP_CFG			0x094

#define QSERDES_V3_COM_DEC_START_MODE0			0x0b0

#define QSERDES_V3_COM_DEC_START_MODE1			0x0b4

#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0		0x0b8

#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0		0x0bc

#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0		0x0c0

#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1		0x0c4

#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1		0x0c8

#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1		0x0cc

#define QSERDES_V3_COM_INTEGLOOP_INITVAL		0x0d0

#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0		0x0d8

#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0		0x0dc

#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1		0x0e0

#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1		0x0e4

#define QSERDES_V3_COM_VCO_TUNE_CTRL			0x0ec

#define QSERDES_V3_COM_VCO_TUNE_MAP			0x0f0

#define QSERDES_V3_COM_VCO_TUNE1_MODE0			0x0f4

#define QSERDES_V3_COM_VCO_TUNE2_MODE0			0x0f8

#define QSERDES_V3_COM_VCO_TUNE1_MODE1			0x0fc

#define QSERDES_V3_COM_VCO_TUNE2_MODE1			0x100

#define QSERDES_V3_COM_VCO_TUNE_INITVAL1		0x104

#define QSERDES_V3_COM_VCO_TUNE_INITVAL2		0x108

#define QSERDES_V3_COM_VCO_TUNE_TIMER1			0x11c

#define QSERDES_V3_COM_VCO_TUNE_TIMER2			0x120

#define QSERDES_V3_COM_CLK_SELECT			0x138

#define QSERDES_V3_COM_HSCLK_SEL			0x13c

#define QSERDES_V3_COM_CORECLK_DIV_MODE0		0x148

#define QSERDES_V3_COM_CORECLK_DIV_MODE1		0x14c

#define QSERDES_V3_COM_CORE_CLK_EN			0x154

#define QSERDES_V3_COM_C_READY_STATUS			0x158

#define QSERDES_V3_COM_CMN_CONFIG			0x15c

#define QSERDES_V3_COM_SVS_MODE_CLK_SEL			0x164

#define QSERDES_V3_COM_DEBUG_BUS0			0x168

#define QSERDES_V3_COM_DEBUG_BUS1			0x16c

#define QSERDES_V3_COM_DEBUG_BUS2			0x170

#define QSERDES_V3_COM_DEBUG_BUS3			0x174

#define QSERDES_V3_COM_DEBUG_BUS_SEL			0x178

#define QSERDES_V3_COM_CMN_MODE				0x184



/* Only for QMP V3 PHY - TX registers */

#define QSERDES_V3_TX_BIST_MODE_LANENO			0x000

#define QSERDES_V3_TX_CLKBUF_ENABLE			0x008

#define QSERDES_V3_TX_TX_EMP_POST1_LVL			0x00c

/* QSERDES V3 TX bits */

# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK		0x001f

# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN		0x0020



#define QSERDES_V3_TX_TX_DRV_LVL			0x01c

# define DP_PHY_TXn_TX_DRV_LVL_MASK			0x001f

# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN			0x0020



#define QSERDES_V3_TX_RESET_TSYNC_EN			0x024

#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN		0x028



#define QSERDES_V3_TX_TX_BAND				0x02c

#define QSERDES_V3_TX_SLEW_CNTL				0x030

#define QSERDES_V3_TX_INTERFACE_SELECT			0x034

#define QSERDES_V3_TX_RES_CODE_LANE_TX			0x03c

#define QSERDES_V3_TX_RES_CODE_LANE_RX			0x040

#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX		0x044

#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX		0x048

#define QSERDES_V3_TX_DEBUG_BUS_SEL			0x058

#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN		0x05c

#define QSERDES_V3_TX_HIGHZ_DRVR_EN			0x060

#define QSERDES_V3_TX_TX_POL_INV			0x064

#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN	0x068

#define QSERDES_V3_TX_LANE_MODE_1			0x08c

#define QSERDES_V3_TX_RCV_DETECT_LVL_2			0x0a4

#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN			0x0c0

#define QSERDES_V3_TX_TX_INTERFACE_MODE			0x0c4

#define QSERDES_V3_TX_VMODE_CTRL1			0x0f0



/* Only for QMP V3 PHY - RX registers */

#define QSERDES_V3_RX_UCDR_FO_GAIN			0x008

#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF			0x00c

#define QSERDES_V3_RX_UCDR_SO_GAIN			0x014

#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF		0x024

#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER		0x028

#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN			0x02c

#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN		0x030

#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034

#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c

#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040

#define QSERDES_V3_RX_UCDR_PI_CONTROLS			0x044

#define QSERDES_V3_RX_RX_TERM_BW			0x07c

#define QSERDES_V3_RX_VGA_CAL_CNTRL1			0x0bc

#define QSERDES_V3_RX_VGA_CAL_CNTRL2			0x0c0

#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB			0x0c8

#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB			0x0cc

#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2		0x0d4

#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3		0x0d8

#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4		0x0dc

#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x0f8

#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x0fc

#define QSERDES_V3_RX_SIGDET_ENABLES			0x100

#define QSERDES_V3_RX_SIGDET_CNTRL			0x104

#define QSERDES_V3_RX_SIGDET_LVL			0x108

#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL		0x10c

#define QSERDES_V3_RX_RX_BAND				0x110

#define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c

#define QSERDES_V3_RX_RX_MODE_00			0x164

#define QSERDES_V3_RX_RX_MODE_01			0x168



/* Only for QMP V3 PHY - PCS registers */

#define QPHY_V3_PCS_POWER_DOWN_CONTROL			0x004

#define QPHY_V3_PCS_TXMGN_V0				0x00c