Commit a8fba64a authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: properly init UVD MC bits on R600 



Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b6a7eeea

drivers/gpu/drm/radeon/r600.c

+4 −0
Original line number Diff line number Diff line
@@ -992,6 +992,8 @@ static int r600_pcie_gart_enable(struct radeon_device *rdev) 
	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
@@ -1042,6 +1044,8 @@ static void r600_pcie_gart_disable(struct radeon_device *rdev) 
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);

	WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);

	radeon_gart_table_vram_unpin(rdev);

}

drivers/gpu/drm/radeon/r600d.h

+3 −1
Original line number Diff line number Diff line
@@ -334,7 +334,7 @@ 
#define MC_VM_AGP_BOT					0x2188

#define	MC_VM_AGP_BASE					0x218C

#define MC_VM_FB_LOCATION				0x2180

#define MC_VM_L1_TLB_MCD_RD_A_CNTL			0x219C

#define MC_VM_L1_TLB_MCB_RD_UVD_CNTL			0x2124

#define 	ENABLE_L1_TLB					(1 << 0)

#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)

#define		ENABLE_L1_STRICT_ORDERING			(1 << 2)
@@ -354,12 +354,14 @@ 
#define		EFFECTIVE_L1_QUEUE_SIZE(x)			(((x) & 7) << 15)

#define		EFFECTIVE_L1_QUEUE_SIZE_MASK			0x00038000

#define		EFFECTIVE_L1_QUEUE_SIZE_SHIFT			15

#define MC_VM_L1_TLB_MCD_RD_A_CNTL			0x219C

#define MC_VM_L1_TLB_MCD_RD_B_CNTL			0x21A0

#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL			0x21FC

#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL			0x2204

#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL			0x2208

#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL			0x220C

#define	MC_VM_L1_TLB_MCB_RD_SYS_CNTL			0x2200

#define MC_VM_L1_TLB_MCB_WR_UVD_CNTL			0x212c

#define MC_VM_L1_TLB_MCD_WR_A_CNTL			0x21A4

#define MC_VM_L1_TLB_MCD_WR_B_CNTL			0x21A8

#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL			0x2210