Commit aa7fd946 authored by Johannes Berg's avatar Johannes Berg Committed by Luca Coelho
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iwlwifi: pcie: remove MSIX_HW_INT_CAUSES_REG_IML handling



This is actually wrong, the bit used here by the image loader
is BIT(1), not BIT(2). The latter will be reused by the new
reset flow soon.

However, as we never had any complaints about not printing
the IML status or not handling the IML error interrupt (and
I suspect the code handling it was incorrectly anyway) just
remove the code for it.

Signed-off-by: default avatarJohannes Berg <johannes.berg@intel.com>
Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/iwlwifi.20201209231352.9a323f4a3493.Ic7aee4dbbf4be42287c338c2fa1b111473724116@changeid


Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent 94631b56
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+1 −1
Original line number Diff line number Diff line
@@ -638,7 +638,7 @@ enum msix_fh_int_causes {
enum msix_hw_int_causes {
	MSIX_HW_INT_CAUSES_REG_ALIVE		= BIT(0),
	MSIX_HW_INT_CAUSES_REG_WAKEUP		= BIT(1),
	MSIX_HW_INT_CAUSES_REG_IML              = BIT(2),
	MSIX_HW_INT_CAUSES_REG_IML              = BIT(1),
	MSIX_HW_INT_CAUSES_REG_CT_KILL		= BIT(6),
	MSIX_HW_INT_CAUSES_REG_RF_KILL		= BIT(7),
	MSIX_HW_INT_CAUSES_REG_PERIODIC		= BIT(8),
+0 −11
Original line number Diff line number Diff line
@@ -2283,17 +2283,6 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
		}
	}

	if (inta_hw & MSIX_HW_INT_CAUSES_REG_IML) {
		/* Reflect IML transfer status */
		int res = iwl_read32(trans, CSR_IML_RESP_ADDR);

		IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res);
		if (res == IWL_IMAGE_RESP_FAIL) {
			isr_stats->sw++;
			iwl_pcie_irq_handle_error(trans);
		}
	}

	/* Chip got too hot and stopped itself */
	if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
		IWL_ERR(trans, "Microcode CT kill error detected.\n");
+0 −1
Original line number Diff line number Diff line
@@ -1103,7 +1103,6 @@ static struct iwl_causes_list causes_list[] = {
	{MSIX_FH_INT_CAUSES_FH_ERR,		CSR_MSIX_FH_INT_MASK_AD, 0x5},
	{MSIX_HW_INT_CAUSES_REG_ALIVE,		CSR_MSIX_HW_INT_MASK_AD, 0x10},
	{MSIX_HW_INT_CAUSES_REG_WAKEUP,		CSR_MSIX_HW_INT_MASK_AD, 0x11},
	{MSIX_HW_INT_CAUSES_REG_IML,            CSR_MSIX_HW_INT_MASK_AD, 0x12},
	{MSIX_HW_INT_CAUSES_REG_CT_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x16},
	{MSIX_HW_INT_CAUSES_REG_RF_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x17},
	{MSIX_HW_INT_CAUSES_REG_PERIODIC,	CSR_MSIX_HW_INT_MASK_AD, 0x18},