Commit ae7169a9 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Add margin on DRR vblank start for subvp



[Description]
- Add margin for HUBP "jitter" for SubVp + DRR case
- Also do a min transition even if MPO is added on a
  non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR)

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2aae5944
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+17 −1
Original line number Diff line number Diff line
@@ -3740,6 +3740,8 @@ static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,

	struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
	bool force_minimal_pipe_splitting = false;
	bool subvp_active = false;
	uint32_t i;

	*is_plane_addition = false;

@@ -3771,11 +3773,25 @@ static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
		}
	}

	for (i = 0; i < dc->res_pool->pipe_count; i++) {
		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
			subvp_active = true;
			break;
		}
	}

	/* For SubVP when adding or removing planes we need to add a minimal transition
	 * (even when disabling all planes). Whenever disabling a phantom pipe, we
	 * must use the minimal transition path to disable the pipe correctly.
	 *
	 * We want to use the minimal transition whenever subvp is active, not only if
	 * a plane is being added / removed from a subvp stream (MPO plane can be added
	 * to a DRR pipe of SubVP + DRR config, in which case we still want to run through
	 * a min transition to disable subvp.
	 */
	if (cur_stream_status && stream->mall_stream_config.type == SUBVP_MAIN) {
	if (cur_stream_status && subvp_active) {
		/* determine if minimal transition is required due to SubVP*/
		if (cur_stream_status->plane_count > surface_count) {
			force_minimal_pipe_splitting = true;
+1 −0
Original line number Diff line number Diff line
@@ -267,6 +267,7 @@ struct dc_caps {
	uint16_t subvp_pstate_allow_width_us;
	uint16_t subvp_vertical_int_margin_us;
	bool seamless_odm;
	uint8_t subvp_drr_vblank_start_margin_us;
};

struct dc_bug_wa {
+1 −0
Original line number Diff line number Diff line
@@ -493,6 +493,7 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,

	pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
	pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
	pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
}

/**
+1 −1
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ struct test_pattern {
	unsigned int cust_pattern_size;
};

#define SUBVP_DRR_MARGIN_US 500 // 500us for DRR margin (SubVP + DRR)
#define SUBVP_DRR_MARGIN_US 600 // 600us for DRR margin (SubVP + DRR)

enum mall_stream_type {
	SUBVP_NONE, // subvp not in use
+1 −0
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@@ -2124,6 +2124,7 @@ static bool dcn32_resource_construct(
	dc->caps.subvp_swath_height_margin_lines = 16;
	dc->caps.subvp_pstate_allow_width_us = 20;
	dc->caps.subvp_vertical_int_margin_us = 30;
	dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin

	dc->caps.max_slave_planes = 2;
	dc->caps.max_slave_yuv_planes = 2;
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