Loading drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h +1 −0 Original line number Diff line number Diff line Loading @@ -19,4 +19,5 @@ int nvkm_falcon_v1_enable(struct nvkm_falcon *); void nvkm_falcon_v1_disable(struct nvkm_falcon *); void gp102_sec2_flcn_bind_context(struct nvkm_falcon *, struct nvkm_memory *); int gp102_sec2_flcn_enable(struct nvkm_falcon *); #endif drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h +1 −0 Original line number Diff line number Diff line Loading @@ -92,6 +92,7 @@ struct nvkm_falcon_func { void (*start)(struct nvkm_falcon *); int (*enable)(struct nvkm_falcon *falcon); void (*disable)(struct nvkm_falcon *falcon); int (*reset)(struct nvkm_falcon *); struct { u32 head; Loading drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c +10 −1 Original line number Diff line number Diff line Loading @@ -47,6 +47,15 @@ gp102_sec2_intr(struct nvkm_sec2 *sec2) } } int gp102_sec2_flcn_enable(struct nvkm_falcon *falcon) { nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001); udelay(10); nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000); return nvkm_falcon_v1_enable(falcon); } void gp102_sec2_flcn_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) Loading Loading @@ -99,7 +108,7 @@ gp102_sec2_flcn = { .clear_interrupt = nvkm_falcon_v1_clear_interrupt, .set_start_addr = nvkm_falcon_v1_set_start_addr, .start = nvkm_falcon_v1_start, .enable = nvkm_falcon_v1_enable, .enable = gp102_sec2_flcn_enable, .disable = nvkm_falcon_v1_disable, .cmdq = { 0xa00, 0xa04, 8 }, .msgq = { 0xa30, 0xa34, 8 }, Loading drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c +1 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,7 @@ gv100_gsp_flcn = { .clear_interrupt = nvkm_falcon_v1_clear_interrupt, .set_start_addr = nvkm_falcon_v1_set_start_addr, .start = nvkm_falcon_v1_start, .enable = nvkm_falcon_v1_enable, .enable = gp102_sec2_flcn_enable, .disable = nvkm_falcon_v1_disable, }; Loading Loading
drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h +1 −0 Original line number Diff line number Diff line Loading @@ -19,4 +19,5 @@ int nvkm_falcon_v1_enable(struct nvkm_falcon *); void nvkm_falcon_v1_disable(struct nvkm_falcon *); void gp102_sec2_flcn_bind_context(struct nvkm_falcon *, struct nvkm_memory *); int gp102_sec2_flcn_enable(struct nvkm_falcon *); #endif
drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h +1 −0 Original line number Diff line number Diff line Loading @@ -92,6 +92,7 @@ struct nvkm_falcon_func { void (*start)(struct nvkm_falcon *); int (*enable)(struct nvkm_falcon *falcon); void (*disable)(struct nvkm_falcon *falcon); int (*reset)(struct nvkm_falcon *); struct { u32 head; Loading
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c +10 −1 Original line number Diff line number Diff line Loading @@ -47,6 +47,15 @@ gp102_sec2_intr(struct nvkm_sec2 *sec2) } } int gp102_sec2_flcn_enable(struct nvkm_falcon *falcon) { nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001); udelay(10); nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000); return nvkm_falcon_v1_enable(falcon); } void gp102_sec2_flcn_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) Loading Loading @@ -99,7 +108,7 @@ gp102_sec2_flcn = { .clear_interrupt = nvkm_falcon_v1_clear_interrupt, .set_start_addr = nvkm_falcon_v1_set_start_addr, .start = nvkm_falcon_v1_start, .enable = nvkm_falcon_v1_enable, .enable = gp102_sec2_flcn_enable, .disable = nvkm_falcon_v1_disable, .cmdq = { 0xa00, 0xa04, 8 }, .msgq = { 0xa30, 0xa34, 8 }, Loading
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c +1 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,7 @@ gv100_gsp_flcn = { .clear_interrupt = nvkm_falcon_v1_clear_interrupt, .set_start_addr = nvkm_falcon_v1_set_start_addr, .start = nvkm_falcon_v1_start, .enable = nvkm_falcon_v1_enable, .enable = gp102_sec2_flcn_enable, .disable = nvkm_falcon_v1_disable, }; Loading