Commit af7cca2a authored by Tomas Winkler's avatar Tomas Winkler Committed by David S. Miller
Browse files

iwlwifi: rename restricted_mem to targ_mem



This patch renames restricted_mem suffix with more proper
name targ_mem for function accessing memory on the nic in target mode

Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent d8609652
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+9 −10
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
 *   ... and set IWL_EVT_DISABLE to 1. */
void iwl_disable_events(struct iwl_priv *priv)
{
	int rc;
	int ret;
	int i;
	u32 base;		/* SRAM address of event log header */
	u32 disable_ptr;	/* SRAM address of event-disable bitmap array */
@@ -157,24 +157,23 @@ void iwl_disable_events(struct iwl_priv *priv)
		return;
	}

	rc = iwl_grab_restricted_access(priv);
	if (rc) {
	ret = iwl_grab_restricted_access(priv);
	if (ret) {
		IWL_WARNING("Can not read from adapter at this time.\n");
		return;
	}

	disable_ptr = iwl_read_restricted_mem(priv, base + (4 * sizeof(u32)));
	array_size = iwl_read_restricted_mem(priv, base + (5 * sizeof(u32)));
	disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
	array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
	iwl_release_restricted_access(priv);

	if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
		IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
			       disable_ptr);
		rc = iwl_grab_restricted_access(priv);
		ret = iwl_grab_restricted_access(priv);
		for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
			iwl_write_restricted_mem(priv,
						 disable_ptr +
						 (i * sizeof(u32)),
			iwl_write_targ_mem(priv,
					   disable_ptr + (i * sizeof(u32)),
					   evt_disable[i]);

		iwl_release_restricted_access(priv);
+9 −9
Original line number Diff line number Diff line
@@ -1657,11 +1657,11 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
	priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
	a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
	for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
		iwl_write_restricted_mem(priv, a, 0);
		iwl_write_targ_mem(priv, a, 0);
	for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
		iwl_write_restricted_mem(priv, a, 0);
		iwl_write_targ_mem(priv, a, 0);
	for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
		iwl_write_restricted_mem(priv, a, 0);
		iwl_write_targ_mem(priv, a, 0);

	iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
		(priv->hw_setting.shared_phys +
@@ -1672,12 +1672,12 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
	for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
		iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
		iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
		iwl_write_restricted_mem(priv, priv->scd_base_addr +
		iwl_write_targ_mem(priv, priv->scd_base_addr +
					SCD_CONTEXT_QUEUE_OFFSET(i),
					(SCD_WIN_SIZE <<
					SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
					SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
		iwl_write_restricted_mem(priv, priv->scd_base_addr +
		iwl_write_targ_mem(priv, priv->scd_base_addr +
					SCD_CONTEXT_QUEUE_OFFSET(i) +
					sizeof(u32),
					(SCD_FRAME_LIMIT <<
@@ -4156,14 +4156,14 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
	tbl_dw_addr = priv->scd_base_addr +
			SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);

	tbl_dw = iwl_read_restricted_mem(priv, tbl_dw_addr);
	tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);

	if (txq_id & 0x1)
		tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
	else
		tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);

	iwl_write_restricted_mem(priv, tbl_dw_addr, tbl_dw);
	iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);

	return 0;
}
@@ -4207,12 +4207,12 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
	/* supposes that ssn_idx is valid (!= 0xFFF) */
	iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);

	iwl_write_restricted_mem(priv,
	iwl_write_targ_mem(priv,
			priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
			(SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
			SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);

	iwl_write_restricted_mem(priv, priv->scd_base_addr +
	iwl_write_targ_mem(priv, priv->scd_base_addr +
			SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
			(SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
			& SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
+4 −5
Original line number Diff line number Diff line
@@ -411,20 +411,19 @@ static inline void iwl_clear_bits_prph(struct iwl_priv
	_iwl_write_prph(priv, reg, (val & ~mask));
}

static inline u32 iwl_read_restricted_mem(struct iwl_priv *priv, u32 addr)
static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
{
	iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, addr);
	return iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT);
}

static inline void iwl_write_restricted_mem(struct iwl_priv *priv, u32 addr,
					    u32 val)
static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
{
	iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr);
	iwl_write_restricted(priv, HBUS_TARG_MEM_WDAT, val);
}

static inline void iwl_write_restricted_mems(struct iwl_priv *priv, u32 addr,
static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
					  u32 len, u32 *values)
{
	iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr);
+15 −15
Original line number Diff line number Diff line
@@ -4457,7 +4457,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
		return;
	}

	count = iwl_read_restricted_mem(priv, base);
	count = iwl_read_targ_mem(priv, base);

	if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
		IWL_ERROR("Start IWL Error Log Dump:\n");
@@ -4470,19 +4470,19 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
	for (i = ERROR_START_OFFSET;
	     i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
	     i += ERROR_ELEM_SIZE) {
		desc = iwl_read_restricted_mem(priv, base + i);
		desc = iwl_read_targ_mem(priv, base + i);
		time =
		    iwl_read_restricted_mem(priv, base + i + 1 * sizeof(u32));
		    iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
		blink1 =
		    iwl_read_restricted_mem(priv, base + i + 2 * sizeof(u32));
		    iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
		blink2 =
		    iwl_read_restricted_mem(priv, base + i + 3 * sizeof(u32));
		    iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
		ilink1 =
		    iwl_read_restricted_mem(priv, base + i + 4 * sizeof(u32));
		    iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
		ilink2 =
		    iwl_read_restricted_mem(priv, base + i + 5 * sizeof(u32));
		    iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
		data1 =
		    iwl_read_restricted_mem(priv, base + i + 6 * sizeof(u32));
		    iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));

		IWL_ERROR
		    ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
@@ -4525,14 +4525,14 @@ static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
	/* "time" is actually "data" for mode 0 (no timestamp).
	 * place event id # at far right for easier visual parsing. */
	for (i = 0; i < num_events; i++) {
		ev = iwl_read_restricted_mem(priv, ptr);
		ev = iwl_read_targ_mem(priv, ptr);
		ptr += sizeof(u32);
		time = iwl_read_restricted_mem(priv, ptr);
		time = iwl_read_targ_mem(priv, ptr);
		ptr += sizeof(u32);
		if (mode == 0)
			IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
		else {
			data = iwl_read_restricted_mem(priv, ptr);
			data = iwl_read_targ_mem(priv, ptr);
			ptr += sizeof(u32);
			IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
		}
@@ -4562,10 +4562,10 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
	}

	/* event log header */
	capacity = iwl_read_restricted_mem(priv, base);
	mode = iwl_read_restricted_mem(priv, base + (1 * sizeof(u32)));
	num_wraps = iwl_read_restricted_mem(priv, base + (2 * sizeof(u32)));
	next_entry = iwl_read_restricted_mem(priv, base + (3 * sizeof(u32)));
	capacity = iwl_read_targ_mem(priv, base);
	mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
	num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
	next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));

	size = num_wraps ? capacity : next_entry;

+17 −17
Original line number Diff line number Diff line
@@ -4785,7 +4785,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
		return;
	}

	count = iwl_read_restricted_mem(priv, base);
	count = iwl_read_targ_mem(priv, base);

	if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
		IWL_ERROR("Start IWL Error Log Dump:\n");
@@ -4793,15 +4793,15 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
			  priv->status, priv->config, count);
	}

	desc = iwl_read_restricted_mem(priv, base + 1 * sizeof(u32));
	blink1 = iwl_read_restricted_mem(priv, base + 3 * sizeof(u32));
	blink2 = iwl_read_restricted_mem(priv, base + 4 * sizeof(u32));
	ilink1 = iwl_read_restricted_mem(priv, base + 5 * sizeof(u32));
	ilink2 = iwl_read_restricted_mem(priv, base + 6 * sizeof(u32));
	data1 = iwl_read_restricted_mem(priv, base + 7 * sizeof(u32));
	data2 = iwl_read_restricted_mem(priv, base + 8 * sizeof(u32));
	line = iwl_read_restricted_mem(priv, base + 9 * sizeof(u32));
	time = iwl_read_restricted_mem(priv, base + 11 * sizeof(u32));
	desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
	blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
	blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
	ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
	ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
	data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
	data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
	line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
	time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));

	IWL_ERROR("Desc               Time       "
		  "data1      data2      line\n");
@@ -4845,14 +4845,14 @@ static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
	/* "time" is actually "data" for mode 0 (no timestamp).
	 * place event id # at far right for easier visual parsing. */
	for (i = 0; i < num_events; i++) {
		ev = iwl_read_restricted_mem(priv, ptr);
		ev = iwl_read_targ_mem(priv, ptr);
		ptr += sizeof(u32);
		time = iwl_read_restricted_mem(priv, ptr);
		time = iwl_read_targ_mem(priv, ptr);
		ptr += sizeof(u32);
		if (mode == 0)
			IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
		else {
			data = iwl_read_restricted_mem(priv, ptr);
			data = iwl_read_targ_mem(priv, ptr);
			ptr += sizeof(u32);
			IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
		}
@@ -4882,10 +4882,10 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
	}

	/* event log header */
	capacity = iwl_read_restricted_mem(priv, base);
	mode = iwl_read_restricted_mem(priv, base + (1 * sizeof(u32)));
	num_wraps = iwl_read_restricted_mem(priv, base + (2 * sizeof(u32)));
	next_entry = iwl_read_restricted_mem(priv, base + (3 * sizeof(u32)));
	capacity = iwl_read_targ_mem(priv, base);
	mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
	num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
	next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));

	size = num_wraps ? capacity : next_entry;