Commit af94e577 authored by Ben Dooks's avatar Ben Dooks Committed by Kukjin Kim
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ARM: S5P64X0: Change to using s3c_gpio_cfgpin_range() 



Change the code setting ranges of GPIO pins using s3c_gpio_cfgpin() to
use the recently introduced s3c_gpio_cfgpin_range().

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
[kgene.kim@samsung.com: modified to s5p64x0 from s5p6440]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 699afb75

arch/arm/mach-s5p64x0/dev-audio.c

+7 −19
Original line number Diff line number Diff line
@@ -24,13 +24,8 @@ static int s5p6440_cfg_i2s(struct platform_device *pdev) 
	/* configure GPIO for i2s port */

	switch (pdev->id) {

	case -1:

		s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5));

		break;



	default:
@@ -47,13 +42,9 @@ static int s5p6450_cfg_i2s(struct platform_device *pdev) 
	switch (pdev->id) {

	case -1:

		s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));

		s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));



		break;



	default:
@@ -116,11 +107,8 @@ static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev) 
{

	switch (pdev->id) {

	case 0:

		s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));

		s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));

		s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));

		s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));

		s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));

		s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2));

		s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2));

		break;



	default: