Commit af981fc2 authored by Tomi Valkeinen's avatar Tomi Valkeinen Committed by Mauro Carvalho Chehab
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media: ti-vpe: cal: remove wait when stopping camerarx 



Asserting ComplexIO reset seems to affect the HW (ie. asserting reset
will break an active capture), but the RESET_DONE bit never changes to
"reset is ongoing" state. Thus we always get a timeout.

Drop the wait, as it seems to achieve nothing.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 3b1fe1ab

drivers/media/platform/ti-vpe/cal-camerarx.c

+2 −13
Original line number Diff line number Diff line
@@ -407,7 +407,6 @@ static int cal_camerarx_start(struct cal_camerarx *phy) 


static void cal_camerarx_stop(struct cal_camerarx *phy)

{

	unsigned int i;

	int ret;



	cal_camerarx_ppi_disable(phy);
@@ -421,19 +420,9 @@ static void cal_camerarx_stop(struct cal_camerarx *phy) 
			CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL,

			CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);



	/* Wait for power down completion */

	for (i = 0; i < 10; i++) {

		if (cal_read_field(phy->cal,

				   CAL_CSI2_COMPLEXIO_CFG(phy->instance),

				   CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==

		    CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING)

			break;

		usleep_range(1000, 1100);

	}

	phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset (%d) %s\n",

	phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset\n",

		phy->instance,

		cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)), i,

		(i >= 10) ? "(timeout)" : "");

		cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)));



	/* Disable the phy */

	cal_camerarx_disable(phy);