Commit b00bf771 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a779g0: Add PWM clock

parent ceb22d93
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+1 −0
Original line number Diff line number Diff line
@@ -175,6 +175,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
	DEF_MOD("msi3",		621,	R8A779G0_CLK_MSO),
	DEF_MOD("msi4",		622,	R8A779G0_CLK_MSO),
	DEF_MOD("msi5",		623,	R8A779G0_CLK_MSO),
	DEF_MOD("pwm",		628,	R8A779G0_CLK_SASYNCPERD4),
	DEF_MOD("scif0",	702,	R8A779G0_CLK_SASYNCPERD4),
	DEF_MOD("scif1",	703,	R8A779G0_CLK_SASYNCPERD4),
	DEF_MOD("scif3",	704,	R8A779G0_CLK_SASYNCPERD4),