Commit b0aedf34 authored by Thierry Reding's avatar Thierry Reding
Browse files

dt-bindings: Add Tegra234 MGBE clocks and resets 



Add the clocks and resets used by the MGBE Ethernet hardware found on
Tegra234 SoCs.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarBhadram Varka <vbhadram@nvidia.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 5de7d31b

include/dt-bindings/clock/tegra234-clock.h

+101 −0
Original line number Diff line number Diff line
@@ -164,10 +164,111 @@ 
#define TEGRA234_CLK_PEX1_C5_CORE		225U

/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */

#define TEGRA234_CLK_PLLC4			237U

/** @brief RX clock recovered from MGBE0 lane input */

#define TEGRA234_CLK_MGBE0_RX_INPUT		248U

/** @brief RX clock recovered from MGBE1 lane input */

#define TEGRA234_CLK_MGBE1_RX_INPUT		249U

/** @brief RX clock recovered from MGBE2 lane input */

#define TEGRA234_CLK_MGBE2_RX_INPUT		250U

/** @brief RX clock recovered from MGBE3 lane input */

#define TEGRA234_CLK_MGBE3_RX_INPUT		251U

/** @brief 32K input clock provided by PMIC */

#define TEGRA234_CLK_CLK_32K			289U

/** @brief Monitored branch of MBGE0 RX input clock */

#define TEGRA234_CLK_MGBE0_RX_INPUT_M		357U

/** @brief Monitored branch of MBGE1 RX input clock */

#define TEGRA234_CLK_MGBE1_RX_INPUT_M		358U

/** @brief Monitored branch of MBGE2 RX input clock */

#define TEGRA234_CLK_MGBE2_RX_INPUT_M		359U

/** @brief Monitored branch of MBGE3 RX input clock */

#define TEGRA234_CLK_MGBE3_RX_INPUT_M		360U

/** @brief Monitored branch of MGBE0 RX PCS mux output */

#define TEGRA234_CLK_MGBE0_RX_PCS_M		361U

/** @brief Monitored branch of MGBE1 RX PCS mux output */

#define TEGRA234_CLK_MGBE1_RX_PCS_M		362U

/** @brief Monitored branch of MGBE2 RX PCS mux output */

#define TEGRA234_CLK_MGBE2_RX_PCS_M		363U

/** @brief Monitored branch of MGBE3 RX PCS mux output */

#define TEGRA234_CLK_MGBE3_RX_PCS_M		364U

/** @brief RX PCS clock recovered from MGBE0 lane input */

#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT		369U

/** @brief RX PCS clock recovered from MGBE1 lane input */

#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT		370U

/** @brief RX PCS clock recovered from MGBE2 lane input */

#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT		371U

/** @brief RX PCS clock recovered from MGBE3 lane input */

#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT		372U

/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */

#define TEGRA234_CLK_MGBE0_RX_PCS		373U

/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */

#define TEGRA234_CLK_MGBE0_TX			374U

/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */

#define TEGRA234_CLK_MGBE0_TX_PCS		375U

/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */

#define TEGRA234_CLK_MGBE0_MAC_DIVIDER		376U

/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */

#define TEGRA234_CLK_MGBE0_MAC			377U

/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */

#define TEGRA234_CLK_MGBE0_MACSEC		378U

/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */

#define TEGRA234_CLK_MGBE0_EEE_PCS		379U

/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */

#define TEGRA234_CLK_MGBE0_APP			380U

/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */

#define TEGRA234_CLK_MGBE0_PTP_REF		381U

/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */

#define TEGRA234_CLK_MGBE1_RX_PCS		382U

/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */

#define TEGRA234_CLK_MGBE1_TX			383U

/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */

#define TEGRA234_CLK_MGBE1_TX_PCS		384U

/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */

#define TEGRA234_CLK_MGBE1_MAC_DIVIDER		385U

/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */

#define TEGRA234_CLK_MGBE1_MAC			386U

/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */

#define TEGRA234_CLK_MGBE1_EEE_PCS		388U

/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */

#define TEGRA234_CLK_MGBE1_APP			389U

/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */

#define TEGRA234_CLK_MGBE1_PTP_REF		390U

/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */

#define TEGRA234_CLK_MGBE2_RX_PCS		391U

/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */

#define TEGRA234_CLK_MGBE2_TX			392U

/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */

#define TEGRA234_CLK_MGBE2_TX_PCS		393U

/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */

#define TEGRA234_CLK_MGBE2_MAC_DIVIDER		394U

/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */

#define TEGRA234_CLK_MGBE2_MAC			395U

/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */

#define TEGRA234_CLK_MGBE2_EEE_PCS		397U

/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */

#define TEGRA234_CLK_MGBE2_APP			398U

/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */

#define TEGRA234_CLK_MGBE2_PTP_REF		399U

/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */

#define TEGRA234_CLK_MGBE3_RX_PCS		400U

/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */

#define TEGRA234_CLK_MGBE3_TX			401U

/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */

#define TEGRA234_CLK_MGBE3_TX_PCS		402U

/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */

#define TEGRA234_CLK_MGBE3_MAC_DIVIDER		403U

/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */

#define TEGRA234_CLK_MGBE3_MAC			404U

/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */

#define TEGRA234_CLK_MGBE3_MACSEC		405U

/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */

#define TEGRA234_CLK_MGBE3_EEE_PCS		406U

/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */

#define TEGRA234_CLK_MGBE3_APP			407U

/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */

#define TEGRA234_CLK_MGBE3_PTP_REF		408U

/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */

#define TEGRA234_CLK_AZA_2XBIT			457U

/** @brief aza_2xbitclk / 2 (aza_bitclk) */

#define TEGRA234_CLK_AZA_BIT			458U



#endif

include/dt-bindings/reset/tegra234-reset.h

+8 −0
Original line number Diff line number Diff line
@@ -30,6 +30,12 @@ 
#define TEGRA234_RESET_I2C7			33U

#define TEGRA234_RESET_I2C8			34U

#define TEGRA234_RESET_I2C9			35U

#define TEGRA234_RESET_MGBE0_PCS		45U

#define TEGRA234_RESET_MGBE0_MAC		46U

#define TEGRA234_RESET_MGBE1_PCS		49U

#define TEGRA234_RESET_MGBE1_MAC		50U

#define TEGRA234_RESET_MGBE2_PCS		53U

#define TEGRA234_RESET_MGBE2_MAC		54U

#define TEGRA234_RESET_PEX2_CORE_10		56U

#define TEGRA234_RESET_PEX2_CORE_10_APB		57U

#define TEGRA234_RESET_PEX2_COMMON_APB		58U
@@ -44,6 +50,8 @@ 
#define TEGRA234_RESET_QSPI0			76U

#define TEGRA234_RESET_QSPI1			77U

#define TEGRA234_RESET_SDMMC4			85U

#define TEGRA234_RESET_MGBE3_PCS		87U

#define TEGRA234_RESET_MGBE3_MAC		88U

#define TEGRA234_RESET_UARTA			100U

#define TEGRA234_RESET_PEX0_CORE_0		116U

#define TEGRA234_RESET_PEX0_CORE_1		117U