Commit b0d0bb1b authored by Daniel Palmer's avatar Daniel Palmer Committed by Arnd Bergmann
Browse files

ARM: mstar: Add Armv7 base dtsi 



Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs.

These SoCs have very similar memory maps and this will avoid
duplicating nodes across multiple dtsis.

Signed-off-by: default avatarDaniel Palmer <daniel@0x0f.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 09220c57

MAINTAINERS

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@@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 
S:	Maintained

W:	http://linux-chenxing.org/

F:	Documentation/devicetree/bindings/arm/mstar.yaml

F:	arch/arm/boot/dts/mstar-v7.dtsi

F:	arch/arm/mach-mstar/









ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT


































arch/arm/boot/dts/mstar-v7.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later









/*









 * Copyright (c) 2020 thingy.jp.









 * Author: Daniel Palmer <daniel@thingy.jp>









 */



















#include <dt-bindings/interrupt-controller/irq.h>









#include <dt-bindings/interrupt-controller/arm-gic.h>



















/ {









	#address-cells = <1>;









	#size-cells = <1>;









	interrupt-parent = <&gic>;



















	cpus {









		#address-cells = <1>;









		#size-cells = <0>;



















		cpu0: cpu@0 {









			device_type = "cpu";









			compatible = "arm,cortex-a7";









			reg = <0x0>;









		};









	};



















	arch_timer {









		compatible = "arm,armv7-timer";









		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)









				| IRQ_TYPE_LEVEL_LOW)>,









			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)









				| IRQ_TYPE_LEVEL_LOW)>,









			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)









				| IRQ_TYPE_LEVEL_LOW)>,









			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)









				| IRQ_TYPE_LEVEL_LOW)>;









		/*









		 * we shouldn't need this but the vendor









		 * u-boot is broken









		 */









		clock-frequency = <6000000>;









	};



















	soc: soc {









		compatible = "simple-bus";









		#address-cells = <1>;









		#size-cells = <1>;









		ranges = <0x16001000 0x16001000 0x00007000>,









			 <0x1f000000 0x1f000000 0x00400000>;



















		gic: interrupt-controller@16001000 {









			compatible = "arm,cortex-a7-gic";









			reg = <0x16001000 0x1000>,









			      <0x16002000 0x2000>,









			      <0x16004000 0x2000>,









			      <0x16006000 0x2000>;









			#interrupt-cells = <3>;









			interrupt-controller;









			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)









					| IRQ_TYPE_LEVEL_LOW)>;









		};



















		riu: bus@1f000000 {









			compatible = "simple-bus";









			reg = <0x1f000000 0x00400000>;









			#address-cells = <1>;









			#size-cells = <1>;









			ranges = <0x0 0x1f000000 0x00400000>;



















			l3bridge: l3bridge@204400 {









				compatible = "mstar,l3bridge";









				reg = <0x204400 0x200>;









			};



















			pm_uart: uart@221000 {









				compatible = "ns16550a";









				reg = <0x221000 0x100>;









				reg-shift = <3>;









				clock-frequency = <172000000>;









				status = "disabled";









			};









		};









	};









};